User's Manual

TRF7970A
www.ti.com SLOS743K –AUGUST 2011–REVISED APRIL 2014
5.4 Handling Ratings
MIN MAX UNIT
T
STG
Storage temperature range -55 150 °C
V
(ESD)
Electrostatic discharge Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
-2 2 kV
Charged-Device Model (CDM), per JEDEC specification JESD22-C101, -500 500 V
all pins
(2)
Machine Model (MM) -200 200 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV
may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V
may actually have higher performance.
5.5 Thermal Characteristics
POWER RATING
(2)
PACKAGE θ
JC
θ
JA
(1)
T
A
≤ 25°C T
A
≤ 85°C
RHB (32 pin) 31°C/W 36.4°C/W 2.7 W 1.1 W
(1) This data was taken using the JEDEC standard high-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-
term reliability.
5.6 Switching Characteristics
TYP operating conditions are T
A
= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DATA_CLK time high or low, one half of
t
LO/HI
Depends on capacitive load on the I/O lines
(1)
250 62.5 50 ns
DATA_CLK at 50% duty cycle
Slave select lead time, slave select low to
t
STE,LEAD
200 ns
clock
Slave select lag time, last clock to slave
t
STE,LAG
200 ns
select high
Slave select disable time, slave select
t
STE,DIS
rising edge to next slave select falling 300 ns
edge
t
SU,SI
MOSI input data setup time 15 ns
t
HD,SI
MOSI input data hold time 15 ns
t
SU,SO
MISO input data setup time 15 ns
t
HD,SO
MISO input data hold time 15 ns
t
VALID,SO
MISO output data valid time DATA_CLK edge to MISO valid, C
L
≤ 30 pF 30 50 75 ns
(1) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400 Ω (12-ns time constant when 30-pF load used).
Copyright © 2011–2014, Texas Instruments Incorporated Specifications 11
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