User's Manual
Table Of Contents
- Contents
- Figures
- Tables
- Document history
- Introduction
- Product concept
- GSM application interface
- GSM/GPRS operating modes
- Power supply
- Power up / down scenarios
- Automatic GPRS Multislot Class change
- Charging control of the GSM part
- Power saving
- Summary of state transitions (except SLEEP mode)
- RTC backup for GSM part of XT55/56
- Serial interfaces of the XT55/56 GSM part
- Audio interfaces
- SIM interface
- Control signals
- GPS application interface
- GSM and GPS antenna interfaces
- Electrical, reliability and radio characteristics
- Mechanics
- Reference approval
- Example applications
- List of parts and accessories
XT55/56 Hardware Interface Description
Confidential / Released
s
XT55/56_hd_v02.06a Page 77 of 125 17.12.2004
Figure 29: Example of LED circuit
4.8 Receiver architecture
The XT55/56 GPS receiver is a product that features the SiRFstarII-Low Power chipset. It is
a complete 12 channel, WAAS-enabled GPS receiver which provides a vastly superior
position accuracy performance. The SiRFstarII architecture builds on the high-performance
SiRFstarI core, adding an acquisition accelerator, differential GPS processor, multipath
mitigation hardware and satellite-tracking engine. The XT55/56 GPS receiver delivers major
advancements in GPS performance, accuracy, integration, computing power and flexibility.
Antenna input
LNA
RF
Filter
GRF2i/LP
RF
Front-End
GSP2e/LP
Signal
Processor
XTAL
Data Bus
Address Bus
GPS-Data
AGC
Clock
Reset IC
FLASH
1MByte
TCXO
GPS_VCC
(+3.3 V DC)
2 x PWRCTL
(RFPC)
GPS_SDI 1
GPS_SDO 1
GPS_SDO 2
GPS_SDI 2
12 x GPS_GPIO
GPS_M-RST
BOOTSELECT
GPS_VANT
GPS_VCC_RF
RECEIVER ARCHITECTURE
RTC
Figure 30: Receiver architecture of the GPS receiver
GPS_RFPC0, GPS_RFPC1
330
Ω
Vcc = 3.3 V DC
BC817
47 k
Ω
GND