User Manual
Table Of Contents
- Document History
- Introduction
- Product Concept
- GSM Application Interface
- GSM/GPRS Operating Modes
- Power Supply
- Power Up / Down Scenarios
- Automatic GPRS Multislot Class Change
- Charging Control of the GSM Part
- Power Saving
- Summary of State Transitions (Except SLEEP Mode)
- RTC Backup for GSM Part of XT55/56
- Serial Interfaces of the XT55/56 GSM Part
- Audio Interfaces
- SIM Interface
- Control Signals
- GPS Application Interface
- GSM and GPS Antenna Interfaces
- Electrical, Reliability and Radio Characteristics
- Mechanics
- Reference Approval
- Example Applications
- List of Parts and Accessories
XT55/56 Hardware Interface Description
Confidential / Preliminary
s
XT55/56_hd_v02.96 Page 78 of 125 18.08.2005
Figure 29: Example of LED circuit
4.8 Receiver Architecture
The XT55/56 GPS receiver is a product that features the SiRFstarII-Low Power chipset. It is
a complete 12 channel, WAAS-enabled GPS receiver which provides a vastly superior
position accuracy performance. The SiRFstarII architecture builds on the high-performance
SiRFstarI core, adding an acquisition accelerator, differential GPS processor, multipath
mitigation hardware and satellite-tracking engine. The XT55/56 GPS receiver delivers major
advancements in GPS performance, accuracy, integration, computing power and flexibility.
Antenna input
LNA
RF
Filter
GRF2i/LP
RF
Front-End
GSP2e/LP
Signal
Processor
XTAL
Data Bus
Address Bus
GPS-Data
AGC
Clock
Reset IC
FLASH
1MByte
TCXO
GPS_VCC
(+3.3 V DC)
2 x PWRCTL
(RFPC)
GPS_SDI 1
GPS_SDO 1
GPS_SDO 2
GPS_SDI 2
12 x GPS_GPIO
GPS_M-RST
BOOTSELECT
GPS_VANT
GPS_VCC_RF
RECEIVER ARCHITECTURE
RTC
Figure 30: Receiver architecture of the GPS receiver
GPS_RFPC0, GPS_RFPC1
330
Ω
Vcc = 3.3 V DC
BC817
47 k
Ω
GND