User Manual
Table Of Contents
- Document History
- Introduction
- Product Concept
- GSM Application Interface
- GSM/GPRS Operating Modes
- Power Supply
- Power Up / Down Scenarios
- Automatic GPRS Multislot Class Change
- Charging Control of the GSM Part
- Power Saving
- Summary of State Transitions (Except SLEEP Mode)
- RTC Backup for GSM Part of XT55/56
- Serial Interfaces of the XT55/56 GSM Part
- Audio Interfaces
- SIM Interface
- Control Signals
- GPS Application Interface
- GSM and GPS Antenna Interfaces
- Electrical, Reliability and Radio Characteristics
- Mechanics
- Reference Approval
- Example Applications
- List of Parts and Accessories
XT55/56 Hardware Interface Description
Confidential / Preliminary
s
XT55/56_hd_v02.96 Page 62 of 125 18.08.2005
Note: Before starting the data transfer the clock GSM_SCLK should be available for at
least three cycles.
After the transfer of the LSB0 the clock GSM_SCLK should be still available for at
least three cycles.
GSM_SLCK
GSM_RFSDAI
GSM_RXDDAI
(input)
Internal
signal
(input)
(input)
Flag
T = 100ns to 5,000 ns
minimum possible distance = 25 bit periods
= T
= T
= T
MSB
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
LSB
0
MSB
15
automatic reset after
reading to DAIRD
interrupt on INTO
after 3 DSP cycles
< 1.5 SCLK
cycles
< 1 DSP cycle
Figure 18: DAI timing on transmit path
GSM_SLCK
GSM_TFSDAI
GSM_TXDDAI
(input)
Internal
signal
(output)
Flag
T = 100ns to 5,000 ns
minimum possible distance = 25 bit periods
= T
= T
= T
MSB
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
LSB
0
MSB
15
interrupt on INTO
after 3 DSP cycles
<1 DSP
cycles
(output)
<2 DSP
cycles
<3 SCLK
cycles
automatic reset after
writing to DAITD
Figure 19: DAI timing on receive path