User's Manual
Table Of Contents
- Document History
- Introduction
- Product Concept
- Application Interface
- Operating Modes
- Power Supply
- Power Up / Power Down Scenarios
- Automatic GPRS Multislot Class Change
- Charging Control
- Summary of State Transitions (Except SLEEP Mode)
- RTC Backup
- SIM Interface
- Serial Interface ASC0
- Serial Interface ASC1
- USB Interface
- I2C Interface
- Audio Interfaces
- Control Signals
- Antenna Interface
- Electrical, Reliability and Radio Characteristics
- Mechanics
- Sample Application
- Reference Approval
- Appendix
TC63 Hardware Interface Description
Strictly confidential / Draft
s
TC63_HD_V00.432 Page 58 of 97 11.05.2005
The timing of a PCM short frame is shown in Figure 24. In PCM mode, 16-bit data are
transferred in both directions at the same time. The duration of a frame sync pulse is one
BITCLK period, starting at the rising edge of BITCLK. TXDAI data is shifted out at the next
rising edge of BITCLK. The most significant bit is transferred first. Data transmitted from
RXDAI of the internal application is sampled at the falling edge of BITCLK.
BITCLK
TXDAI
RXDAI
FS
MSB
MSB
LSB
LSB
14 13
14 13
1
1
12
12
2
2
LSB1
1
LSB
MSB 14
MSB 14
125µs
Figure 24: PCM timing