User's Manual

Cinterion
®
PLAS9-X Hardware Interface Overview
Figures
39
 PLAS9-X_HIO_v00.044 2017-09-19
Confidential / Preliminary
Page 5 of 39
Figures
Figure 1: PLAS9-X system overview............................................................................... 9
Figure 2: USB circuit ..................................................................................................... 10
Figure 3: First UICC/SIM/USIM interface ...................................................................... 12
Figure 4: Second UICC/SIM/USIM interface................................................................. 12
Figure 5: Embedded Stripline line arrangement............................................................ 17
Figure 6: Micro-Stripline line arrangement samples...................................................... 18
Figure 7: Routing to application‘s RF connector ........................................................... 19
Figure 8: Routing to PLAS9-X evaluation module‘s RF connector................................ 20
Figure 9: PLAS9-X sample application.......................................................................... 22
Figure 10: Decoupling capacitor(s) for BATT+................................................................ 24
Figure 11: PLAS9-X – top and bottom view .................................................................... 25
Figure 12: Dimensions of PLAS9-X (all dimensions in mm)............................................ 26
Figure 13: Reference equipment for type approval......................................................... 30