User's Manual

PCS3_HD_v01.000-03
Confidential / Preliminary
Page 35 of 101
2013-10-21
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PCS3 Hardware Interface Description
3.5 RTC Backup
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SMT
inte
r
face
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3.5 RTC Backup
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The internal Real Time Clock of PCS3 is supplied from a separate voltage regulator in the pow-
er supply component which is also active when PCS3 is in Power Down mode and BATT+ is
available.
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In addition, you can use the VDDLP line on the SMT interface to backup the RTC from an ex-
ternal capacitor or a battery (rechargeable or non-chargeable). The capacitor is charged from
the internal LDO of PCS3. If the voltage supply at BATT+ is disconnected the RTC can be pow-
ered by the capacitor. The size of the capacitor determines the duration of buffering when no
voltage is applied to PCS3, i.e. the greater the capacitor the longer PCS3 will save the date and
time. It limits the output current of an empty capacitor or battery.
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Figure 8 show various sample configurations.
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Module
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Non chargeable battery
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BATT+
Chargeable battery
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Capacitor
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3.2V
LDO
0.8k
1k
VDDLP
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or or
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Processor and power
management
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RTC
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GND
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Figure 8: RTC supply variants