User's Manual

PCS3_HD_v01.000-03
Confidential / Preliminary
Page 20 of 101
2013-10-21
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PCS3 Hardware Interface Description
2.2 PCS3 System Overview
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2.3 Circuit Concept
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Figure 2 shows a block diagram of the PCS3 module and illustrates the major functional com-
ponents:
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Baseband block:
• CDMA controller/transceiver/power supply
• NOR Flash/pSRAM memory with multiplexed address data bus
• Audio codec
• Application interface (SMT with connecting pads)
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RF section:
• RF transceiver
• RF power amplifier/frontend
• RF filter
• Antenna pad
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Figure 2: PCS3 block diagram
Interface
(USB, UART, I2C, CSIM)
156 pad
LGA
BATT+
BATT+_CDMA
BC1 PA
PRX_MB2
TX_MB1
Diplexer
BC1
Duplexer
64Mb pSRAM
128Mb NOR flash memory
MCP Memory
EBI1
QSC1105
JTAG
BC0, BC10
PA
BC0, BC10
Duplexer
PRX_LB1
TX_LB1
GPIO
CDMA2000 BC0, BC10
BC0, BC10 TX: 817-849 MHz
BC0, BC10 RX: 862-894 MHz
CDMA2000 BC1
TX: 1850-1910 MHz
RX: 1930-1990 MHz
Analog Audio Interface
(MICP, MICN, EPP, EPN)
ADCx_in
Digital Audio Interface
VEXT
IGT, EMERG_OFF
PWR_IND, STATUS
To PA
To QSC1105 Digtal Core
To QSC1105 RX ADC, RF1
To Memory, QSC1105 digital P1, VEXT,
To QSC1105 digital P4
19.2MHz
Xtal
2.85V
1.8V
2.2V
1.3V
To QSC1105 RF2
To QSC1105 TX, RX ADC
To QSC1105 digital P3
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