User's Manual
Table Of Contents
- Contents
- Figures
- Tables
- Document History
- Introduction
- Product concept
- Application Interface
- Antenna interface
- Electrical, reliability and radio characteristics
- Mechanics
- Reference Approval
- List of parts and accessories
MC46 Hardware Interface Description
DRAFT
MC46_HD_V02.8xb Page 54 of 98 21.08.2003
Note: Before starting the data transfer the clock SCLK should be available for at least
three cycles.
After the transfer of the LSB0 the clock SCLK should be still available for at least
three cycles.
SLCK
RFSDAI
RXDDAI
(input)
Internal
signal
(input)
(input)
Flag
T = 100ns to 5,000 ns
Figure 18: DAI timing on transmit path
SLCK
TFSDAI
TXDDAI
(input)
Internal
signal
(output)
(output)
Flag
T = 100ns to 5,000 ns
Figure 19: DAI timing on receive path