User's Manual

MC46 Hardware Interface Description
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MC46_HD_V03.05 Page 53 of 99 13.11.2003
3.10.2 Speech processing
The speech samples from the ADC or DAI are handled by the DSP of the baseband
controller to calculate e.g. amplifications, sidetone, echo cancellation or noise suppression
depending on the configuration of the active audio mode. These processed samples are
passed to the speech encoder. Received samples from the speech decoder are passed to
the DAC or DAI after post processing (frequency response correction, adding sidetone etc.).
Full rate, half rate, enhanced full rate, adaptive multi rate (AMR), speech and channel
encoding including voice activity detection (VAD) and discontinuous transmission (DTX) and
digital GMSK modulation are also performed on the GSM baseband processor.
Customer specific audio parameters can be evaluated and supplied by Siemens on request.
These parameters can be downloaded to MC46 using an AT command. For further
information refer to [8] or contact your Siemens distributor.
3.10.3 DAI timing
To support the DAI function, MC46 integrates a simple five-line serial interface with one input
data clock line (SCLK) and input / output data and frame lines (TXDDAI, TFSDAI, RXDDAI,
RFSDAI).
The serial interface is always active if the external input data clock SLCK is present, i.e. the
serial interface is not clocked by the DSP of the MC46 baseband processor. SLCK must be
supplied from the application and can be in a frequency range between 0.2 and 10 MHz.
Serial transfer of 16-bit words is done in both directions.
Data transfer to the application is initiated by the module through a short pulse of TFSDAI.
The duration of the TFSDAI pulse is one SCLK period, starting at the rising edge of SLCK.
During the following 16 SLCK cycles, the 16-bit sample will be transferred on the TXDDAI
line. The next outgoing sample will be transferred after the next TFSDAI pulse which occurs
every 125 µs.
The TFSDAI pulse is the master clock of the sample transfer. From the rising edge of the
TFSDAI pulse, the application has 100 µs to transfer the 16-bit input sample on the RXDDAI
line. The rising edge of the RFSDAI pulse (supplied by the application) may coincide with the
falling edge of TFSDAI or occur slightly later - it is only significant that, in any case, the
transfer of the LSB input sample will be completed within the specified duration of 100 µs.
Audio samples are transferred from the module to the application in an average of 125µs.
This is determined by the 8kHz sampling rate, which is derived from and synchronized to the
GSM network. As SLCK is independent of the GSM network, the distance between two
succeeding sample transfers may vary about +
1 SLCK period.
The application is required to adapt its sampling rate to the TFSDAI rate. Failure to
synchronize the timing between the module and the application may cause audible pops and
clicks in a conversation. The timing characteristics of both data transfer directions are shown
in Figure 18 and Figure 19.