User's Manual
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.1.1 Pad Assignment
- 2.1.2 Signal Properties
- 2.1.3 USB Interface
- 2.1.4 Serial Interface ASC0
- 2.1.5 Serial Interface ASC1
- 2.1.6 UICC/SIM/USIM Interface
- 2.1.7 Digital Audio Interface
- 2.1.8 Pulse Code Modulation Interface (PCM)
- 2.1.9 Inter IC Sound Interface (I2S)
- 2.1.10 GPIO Interface
- 2.1.11 I2C Interface
- 2.1.12 SPI Interface
- 2.1.13 Pulse Counter
- 2.1.14 HSIC Interface (ELS51-VA Only)
- 2.1.15 SDIO Interface (ELS51-VA Only)
- 2.1.16 Control Signals
- 2.2 RF Antenna Interface
- 2.3 Sample Application
- 2.1 Application Interface
- 3 Operating Characteristics
- 3.1 Operating Modes
- 3.2 Power Up/Power Down Scenarios
- 3.3 Power Saving
- 3.4 Power Supply
- 3.5 Operating Temperatures
- 3.6 Electrostatic Discharge
- 3.7 Blocking against RF on Interface Lines
- 3.8 Reliability Characteristics
- 4 Mechanical Dimensions, Mounting and Packaging
- 5 Regulatory and Type Approval Information
- 6 Document Information
- 7 Appendix
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ELS31-VA/ELS51-VA Hardware Interface Description
4.2 Mounting ELS31-VA/ELS51-VA onto the Application Platform
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ELS31-VA_ELS51-VA_HID_v01.000 2017-01-04
Confidential / Preliminary
Page 79 of 106
4.2 Mounting ELS31-VA/ELS51-VA onto the Application Plat-
form
This section describes how to mount ELS31-VA/ELS51-VA onto the PCBs (=printed circuit
boards), including land pattern and stencil design, board-level characterization, soldering con-
ditions, durability and mechanical handling. For more information on issues related to SMT
module integration see also [4].
Note: To avoid short circuits between signal tracks on an external application's PCB and vari-
ous markings at the bottom side of the module, it is recommended not to route the signal tracks
on the top layer of an external PCB directly under the module, or at least to ensure that signal
track routes are sufficiently covered with solder resist.
4.2.1 SMT PCB Assembly
4.2.1.1 Land Pattern and Stencil
The land pattern and stencil design as shown below is based on Gemalto characterizations for
lead-free solder paste on a four-layer test PCB and a 120 micron thick stencil.
The land pattern given in Figure 43 reflects the module‘s pad layout, including signal pads and
ground pads (for pad assignment see Section 2.1.1).
Figure 43: Land pattern (top view)