User's Manual

Cinterion
®
ELS31-/ELS51-US Hardware Interface Overview
2.1 Application Interface
29
 ELS31-US_ELS51-US_HIO_v01.000a 2016-12-28
Confidential / Preliminary
Page 17 of 46
2.1.6 I
2
C Interface
I
2
C is a serial, 8-bit oriented data transfer bus for bit rates up to 100kbps. It consists of two lines,
the serial data line I2CDAT and the serial clock line I2CCLK. The module acts as a single mas-
ter device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-directional line. Each
device connected to the bus is software addressable by a unique 7-bit address, and simple
master/slave relationships exist at all times. The module operates as master-transmitter or as
master-receiver. The customer application transmits or receives data only on request of the
module.
The I
2
C interface can be powered via the V180 line of ELS31-US/ELS51-US. If connected to
the V180 line, the I
2
C interface will properly shut down when the module enters the Power
Down mode.
Note: Good care should be taken when creating the PCB layout of the host application: The
traces of I2CCLK and I2CDAT should be equal in length and as short as possible.
2.1.7 SPI Interface
The ELS31-US/ELS51-US GPIO interface lines can be configured as Serial Peripheral Inter-
face (SPI). The SPI is a synchronous serial interface for control and data transfer between
ELS31-US/ELS51-US and the external application. Only one application can be connected to
the SPI and the interface supports only master mode. The transmission rates are up to 6.5Mbit/
s. The SPI interface comprises the two data lines SPI_MOSI and SPI_MISO, the clock line
SPI_CLK a well as the chip select lines SPI_CS1 and SPI_CS2.
2.1.8 Pulse Counter
The GPIO8 line can be configured as pulse counter line COUNTER (for GPIOs see Section
2.1.5). The pulse counter interface can be used, for example, as a clock - it is designed to mea-
sure signals from 0 to 1000 pulses per second. Note that the pulse counter works in batches
of 8 pulses, i.e., the URC indicates the number of pulses counted in batches of 8 pulses. For
more information on how to use this feature see [1].
2.1.9 HSIC Interface (ELS51-US Only)
The (USB) High Speed Inter Chip (HSIC) interface can be used between the module and an
external application processor, and is compliant to the High Speed USB 2.0 interface with
480Mbit/s. The maximum distance between module processor and external application proces-
sor should not exceed 100mm.
The HSIC interface comprises two signal lines (strobe - HSIC_STRB - and data - HSIC_DATA)
used in a source synchronous serial interface with a 240MHz clock to provide a 480Mbps USB
interface. The HSIC_STRB and HSIC_DATA lines are high-speed signals and should be rout-
ed as 50Ohm impedance traces. The trace length of these signals should be balanced to min-
imize timing skew and be no longer than 100mm.
The HSIC interface implementation complies with the USB HSIC standard “High-Speed Inter-
Chip USB Electrical Specification”, Version 1, September 23, 2007
1
.
1. The USB specifications are ready for download on http://www.usb.org/developers/docs/usb20_docs/