Data Sheet

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03.10GFA-1103A
XMCV5 Virtex-5 processor with QDR2 and DDR2 memory
Block Diagram
Ordering Information
Specifications
Xilinx Virtex-5 FPGA
• FX100T,SX95TorLX110Tbuildoptions
External Memory
• 144MbitsQDR2SRAM
• 512MBytesDDR2SDRAM
• 384Mbitsuser&congurationFLASH
Rear I/O
• VITA42.3PCIe(standard)or
• VITA42.2sRIObuildoption
• 16xRocketI/O,20LVDS,28GPIO,
2xGbERGMII&5GPIO(3V3),
2xRS232/422,I2CBus
Front I/O
• 80pinheader:
• 2xGbE(RGMII),2xRS232/422,28LVDS,24GPIO&
5GPIO(3v3),JTAG
XMCV5TST
• Frontpanelbreak-outmoduleforSWdevelopment
Form Factor
• RuggedVITA42.0formfactorforair,andconduction
cooled systems
XMCV5VWRAP:
• EDKandISEprojectwithtestedcores
• QuickstartFPGAimage
Virtex 5
FX100T, SX95T or LX110T
Serial Flash
128 Mbit x3
I/O Header
Ethernet RGMII Logic Analyzer LVDS RS232
DDR2 SDRAM
64M x32
QDR2 SRAM
2M x36
Power
Manager
Clock
Generator
CPLD
RocketIO
XMC P15
BMM
DDR2 SDRAM
64M x32
QDR2 SRAM
2M x36
Configuration/
General Purpose
LVDS GPIO
PMC P14
RocketIO
XMC P16
JTAG
JTAG
JTAG
SPI
SPI
Clocks
267 MHz
300 MHz
267 MHz
300 MHz
5
8648
XMCV5 - 1 1 P 2 1 1
1 = Quick Start Image
1 = VITA42.3 - PCIe
2 = VITA42.2 - sRIO
0 = No external SRAM or SDRAM
2 = 144 Mbits SRAM & 512 MBytes SDRAM
P = FX100T
S = SX95T
L = LX110T
0 = Standard heat sink
1 = no heat sink
Build level 1 to 5