Data Sheet

About GE Intelligent Platforms
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07.10GFA-949A
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www.ge-ip.com/sensorprocessing
ICS-8551-Rugged4/2-channel,1.5/3GHzADCPMC/XMCModulewithVirtex-4FPGA
Specifications
Analog Input
• FourAC-coupledanaloginputs
• 50Ohminputimpedance
• Softwareselectablefullscaleinput,0.236dBm
(650mVpp)or2.768dBm(870mVpp)
• Inputsignalbandwidthof2MHz–700MHz
(-3dBpoint)
• Maximumsamplerateof1.5GSPS/channelin4channel
modeor3.0GSPS/channelin2channelmode
• Minimumsamplerateof200MSPS
• InternalSampleClockVCOlockedtoonboard
10MHzTCXOorExternalSource
• Analogtodigitalresolution8bits
• Samplingonrisingorfallingedgeofinternalor
externalsampleclock
• ExternalClockLVTTLorSinewavecompatible
0dBmmin.,20dBmmax.
• ExternalTriggerLVTTL
• ExternalSyncLVTTL
• ExternalUserLVTTL
• SINAD>40dB@748MHzinputfrequency
• SFDR>45dB@748MHzinputfrequency
General Specifications
• IEEEStd.P1386.1-2001compatiblePCImezzaninecard
• ANSI/VITA20-2001conduction-cooledPMC
• VITA42XMCcompatible(singleconnector)
• VxWorks,LinuxandWindowssoftwaredevicedrivers
Onboard Resources
• XilinxVirtex-4FPGAFX60
• TCXO@10MHz
• 8-plugSamtecGRF1-Jconnector(Ruggedization
levels1,2and3)
• 8individualMMCXCoaxialconnectors(Ruggediza-
tionlevels4and5)
I/O Specifications
• PCI2.264-bit,66MHzmaster/targetburstmode
DMAcapable
• XMCinterface,twochannels,eachwithfourlanes
@3.125GBytes/sVITA42.0-200x
• All64userprogrammableI/OviaPn4connector
routeddirectlytoFPGA
• Pn4userdenableLVDSorLVTTLsignallevels
Environmental
• Fivebuildlevelsavailable.Airandconduction
cooledversions
• -40°Cto+85°Coperatingtemperature
• 95%non-condensinghumidity
Ordering Information
ICS-8551A-xOO
ICS-8551withVirtex-4FX60FPGA
DRV-8551-VXW
SoftwaredevicedriverforVxWorksoperatingsystem
DRV-8551-LX
SoftwaredevicedriverforLinuxoperatingsystem
DRV-8551-WIN
SoftwaredevicedriverforWindowsoperatingsystem
DRV-8551-SCA
SCAcompliantdriver
HDK-8551
HardwareDevelopmentKitforFPGAdevelopmentbyuser,includingdefaultcoreanddual-channel
programmableDDCcore
Block Diagram
CH1
CH2
CH3
CH4
Clock
Trigger
Sync.
User
Ref. Oscillator
User FPGA
Virtex
(FX60)
P4
user
IO
PCI
2.2
Interface
64/66
XMC
Rocket
IO
PMC
XMC
connectors
Dual
ADC
Clock Control
Sample Rate
3 GSPS
1.5 GSPS
Channel Use
1 and 3 only
1,2,3 and 4
Dual
ADC