Instructions

7
I2C Protocol Operation
The I2C serial bus protocol operates as follows:
1
The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The
following byte is the address byte, which consists of the 7-bit slave address followed by a read/write bit with a zero state indicating a write request. A write
operation is used as the initial stage of both read and write transfers. If the slave address corresponds to the module’s address the unit responds by pulling
SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device
waits for data to be written to or read from its shift register.
2
Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line
must occur during the low period of SCL and remain stable during the high period of SCL.
3
An 8 bit data byte following the address loads the I2C control register with the address of the rst control register to be read along with ags indicating if auto
increment of the addressed control register is desired with successive reads or writes; and if access to the internal micro or external correlation processor
register space is requested. Bit locations 5:0 contain the control register address while bit 7 enables the automatic incrementing of control register with
successive data blocks. Bit position 6 selects correlation memory external to the microcontroller if set. (Presently an advanced feature)
4
If a read operation is requested, a stop bit is issued by the master at the completion of the rst data frame followed by the initiation of a new start condition,
slave address with the read bit set (one state). The new address byte is followed by the reading of one or more data bytes succession. After the slave has
acknowledged receipt of a valid address, data read operations proceed by the master releasing the I2C data line SDA with continuing clocking of SCL. At the
completion of the receipt of a data byte, the master must strobe the acknowledge bit before continuing the read cycle.
5
For a write operation to proceed, Step 3 is followed by one or more 8 bit data blocks with acknowledges provided by the slave at the completion of each
successful transfer. At the completion of the transfer cycle a stop condition is issued by the master terminating operation.
Register Denitions
Control Register List
Address R/W Name Description Intial Value Details
0x00 W ACQ_COMMAND Device command -- page 8
0x01 R STATUS System status -- page 8
0x02 R/W SIG_COUNT_VAL Maximum acquisition count 0x80 page 8
0x04 R/W ACQ_CONFIG_REG Acquisition mode control 0x08 page 8
0x09 R VELOCITY Velocity measurement output -- page 8
0x0c R PEAK_CORR Peak value in correlation record -- page 8
0x0d R NOISE_PEAK Correlation record noise oor -- page 8
0x0e R SIGNAL_STRENGTH Received signal strength -- page 9
0x0f R FULL_DELAY_HIGH Distance measurement high byte -- page 9
0x10 R FULL_DELAY_LOW Distance measurement low byte -- page 9
0x11 R/W OUTER_LOOP_COUNT Burst measurement count control 0x01 page 9
0x12 R/W REF_COUNT_VAL Reference acquisition count 0x05 page 9
0x14 R LAST_DELAY_HIGH Previous distance measurement high byte -- page 9
0x15 R LAST_DELAY_LOW Previous distance measurement low byte -- page 9
0x16 R UNIT_ID_HIGH Serial number high byte Unique page 9
0x17 R UNIT_ID_LOW Serial number low byte Unique page 9
0x18 W I2C_ID_HIGH Write serial number high byte for I2C address unlock -- page 9
0x19 W I2C_ID_LOW Write serial number low byte for I2C address unlock -- page 9
0x1a R/W I2C_SEC_ADDR Write new I2C address after unlock -- page 9
0x1c R/W THRESHOLD_BYPASS Peak detection threshold bypass 0x00 page 9
0x1e R/W I2C_CONFIG Default address response control 0x00 page 9
0x40 R/W COMMAND State command -- page 10
0x45 R/W MEASURE_DELAY Delay between automatic measurements 0x14 page 10
0x4c R PEAK_BCK Second largest peak value in correlation record -- page 10
0x52 R CORR_DATA Correlation record data low byte -- page 10
0x53 R CORR_DATA_SIGN Correlation record data high byte -- page 10
0x5d R/W ACQ_SETTINGS Correlation record memory bank select -- page 10
0x65 R/W POWER_CONTROL Power state control 0x80 page 10