User's Manual
Table Of Contents
- Table of Contents
- About This Manual
- Chapter 1 GS2100M Overview
- Chapter 2 GS2100M Architecture
- Chapter 3 Pin-out and Signal Description
- Chapter 4 Electrical Characteristics
- Chapter 5 Package and Layout Guidelines
GS2100M Low Power WiFi Module Data Sheet Electrical Characteristics
Sigma Delta ADC Parameters
GS2100M-DS-001212, Release 0.8 Confidential Preliminary 47
2. Full scale (FS) can be trimmed in the reference generator. The gain error specified is on top
of the reference level error.
3. The master clock frequency is always 250 times higher than data clock rate.
4. Assumes a -1 dB full scale input and corrected for full scale. Fin can be from 0 to 10KHz.
The SNR is met for all master clock frequencies.
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