Data Sheet

6
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace
buffering
Unified trace capability for Quad Cortex®-A53 and Cortex®-M7 CPUs
Cross Triggering Interface (CTI)
Support for 4-pin (JTAG) debug interface
DDR3L
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data
strobe
All addresses and control inputs except data, data strobes and data
masks latched on the rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10, 11 and 13 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8
Programmable burst length 4/8 with both nibble sequential and interleave
mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- 7.8 μs at 0°C ~ 85 °C
- 3.9 μs at 85°C ~ 95 °C
Driver strength selected by EMRS
Dynamic On Die Termination supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
eMMC
Packaged NAND flash memory with e•MMC™ 5.1 interface
Compliant with e•MMC™ Specification Ver.4.4, 4.41,4.5,5.0 & 5.1