MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT DISK DRIVES PRODUCT MANUAL C141-E045-02EN
REVISION RECORD Edition Date published 01 August., 1997 02 March, 1998 Revised contents All pages revised. Specification No.: C141-E045-**EN The contents of this manual is subject to change without prior notice. All Rights Reserved.
PREFACE This manual describes the MPB3021AT/MPB3032AT/MPB3043AT/MPB3052AT/MPB3064AT, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.
Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazarous situation likely to result in serious personal injury if the user does not perform the procedure correctly.
LIABILITY EXCEPTION "Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
CONTENTS page CHAPTER 1 DEVICE OVERVIEW ................................................................................... 1 - 1 1.1 Features .......................................................................................................................... 1 - 1 1.1.1 Functions and performance ............................................................................................ 1 - 1 1.1.2 Adaptability....................................................................................
3.4.1 Location of setting jumpers ............................................................................................ 3 - 9 3.4.2 Factory default setting .................................................................................................... 3 - 10 3.4.3 Jumper configuration...................................................................................................... 3 - 10 CHAPTER 4 THEORY OF DEVICE OPERATION.........................................................
5.2.2 Command block registers ............................................................................................... 5 - 8 5.2.3 Control block registers ................................................................................................... 5 - 13 5.3 Host Commands ............................................................................................................. 5 - 13 5.3.1 Command code and parameters....................................................................
5.6.4.5 Device terminating an Ultra DMA data in burst ............................................................. 5 - 83 5.6.4.6 Host terminating an Ultra DMA data in burst................................................................. 5 - 84 5.6.4.7 Initiating an Ultra DMA data out burst........................................................................... 5 - 85 5.6.4.8 Sustained Ultra DMA data out burst............................................................................... 5 - 86 5.6.4.
FIGURES page 1.1 Current fluctuation (Typ.) when power is turned on....................................................... 1 - 7 2.1 Disk drive outerview ...................................................................................................... 2 - 1 2.2 Configuration of disk media heads................................................................................. 2 - 3 2.3 1 drive system configuration ....................................................................................
5.4 Protocol for command abort ........................................................................................... 5 - 58 5.5 WRITE SECTOR(S) command protocol........................................................................ 5 - 59 5.6 Protocol for the command execution without data transfer ............................................ 5 - 60 5.7 Normal DMA data transfer ............................................................................................. 5 - 62 5.
TABLES page 1.1 Specifications ................................................................................................................. 1 - 4 1.2 Model names and product numbers................................................................................ 1 - 5 1.3 Current and power dissipation........................................................................................ 1 - 6 1.4 Environmental specifications........................................................................
CHAPTER 1 DEVICE OVERVIEW 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects Overview and features are described in this chapter, and specifications and power requirement are described. The MPB3021AT/MPB3032AT/MPB3043AT/MPB3052AT/MPB3064AT are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is compact and reliable. 1.
(4) Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 10 ms (at read). 1.1.2 Adaptability (1) Power save mode The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor. (2) Wide temperature range The disk drive can be used over a wide temperature range (5°C to 55°C).
(5) Error correction and retry by ECC If a recoverable error occurs, the disk drive itself attempts error recovery. The 18-byte ECC has improved buffer error correction for correctable data errors. (6) Write cache When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media. This feature reduces the access time at writing.
1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drive. Table 1.1 Formatted Capacity (*1) Number of Heads Specifications MPB3021AT MPB3032AT MPB3043AT MPB3052AT MPB3064AT 2162.76 MB 3243.66 MB 4325.52 MB 5249.66 MB 6488.29 MB 2 3 4 5 6 Number of Cylinders (User + Alternate & SA) 8,983 + 123 Bytes per Sector 512 Recording Method 8/9 PRML Track Density 9531 TPI Bit Density 161,815 BPI Rotational Speed 5400 rpm ± 0.
1.2.2 Model and product number Table 1.2 lists the model names and product numbers. Table 1.2 Model Name Capacity (user area) Mounting Screw Order No. MPB3021AT 2162.76 No. 6-32UNC CA01630-B321 MPB3032AT 3243.66 No. 6-32UNC CA01630-B331 MPB3043AT 4325.52 No. 6-32UNC CA01630-B341 MPB3052AT 5249.66 No. 6-32UNC CA01630-B351 MPB3064AT 6488.29 No. 6-32UNC CA01630-B361 1.
Table 1.3 Typical RMS current (*1) [mA] Mode of Operation Model Current and power dissipation +12 V MPB 3021AT Spin up MPB 3032AT MPB 3043AT MPB 3052AT MPB 3064AT 1300 1500 peak Idle (Ready) (*3) Typical Power (*2) [watts] +5 V All Models MPB 3021AT MPB 3032AT MPB 3043AT 460 600 peak MPB 3052AT MPB 3064AT 17.9 115 140 185 460 3.68 3.98 4.52 R/W (On Track) (*4) 125 150 200 510 4.05 4.35 4.95 Seek (Random) (*5) 335 360 410 510 6.57 6.87 7.47 Standby 4 155 0.
(4) Current fluctuation (Typ.) when power is turned on Note: Maximum current is 1.5 A and is continuance is 1.5 seconds Figure 1.1 (5) Current fluctuation (Typ.) when power is turned on Power on/off sequence The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abnormal. This prevents data from being destroyed and eliminates the need to be concerned with the power on/off sequence.
1.4 Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.
1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.6 Shock and vibration specification Vibration (swept sine, one octave per minute) • Operating • Non-operating Shock (half-sine pulse, 11 ms duration) • Operating • Non-operating 5 to 300 Hz, 0.5G-0-peak (without non-recovered errors) 5 to 400 Hz, 4G-0-peak (no damage) 10G (without non-recovered errors) 75G (no damage) 1.
(4) Data assurance in the event of power failure Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment). 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below.
CHAPTER 2 2.1 DEVICE CONFIGURATION 2.1 Device Configuration 2.2 System Configuration Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter. Figure 2.
(1) Disk The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 40,000 start/stop operations. MPB3021AT: MPB3032AT: MPB3043AT: MPB3052AT: MPB3064AT: (2) 1 disk 2 disks 2 disks 3 disks 3 disks Head The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts. Figure 2.
MPB3021AT Model MPB3021 Model Spindle Actuator 1 0 MPB3032AT Model MPB3032AT Model MPB3043AT Model Model Spindle Actuator Spindle Actuator 3 2 2 1 1 0 0 MPB3052AT MPB3052AT Model MPB3064AT Model Model Spindle Actuator Spindle Actuator 5 4 3 4 3 2 1 2 1 0 0 Figure 2.2 (3) Configuration of disk media heads Spindle motor The disks are rotated by a direct drive Hall-less DC motor.
(5) Air circulation system The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure. (6) Read/write circuit The read/write circuit uses a LSI chip for the read/write preamplifier.
2.2.3 2 drives connection HA (Host adaptor) Host Disk drive #0 AT bus (Host interface) Disk drive #1 ATA interface Note: When the drive that is not conformed to ATA is connected to the disk drive is above configuration, the operation is not guaranteed. Figure 2.4 2 drives configuration IMPORTANT HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-3 interface.
CHAPTER 3 3.1 INSTALLATION CONDITIONS 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm.
Figure 3.
3.2 Mounting (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. The mounting angle can vary ±5° from the horizontal. gravity (a) Horizontal mounting (b) Vertical mounting –1 Figure 3.2 (2) (c) Vertical mounting –2 Orientation Frame The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also connected to signal ground. These are electrically shorted. Note: Use No.
Use these screw holes Do not use this screw holes Figure 3.3 Limitation of side-mounting Side surface mounting 2.5 Bottom surface mounting 2.5 DE DE 2.5 2 PCA A Frame of system cabinet 4.5 or less Screw Screw 5.0 or less Details of A Details of B Figure 3.
(4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface temperature from exceeding 60°C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling. To check the cooling efficiency, measure the surface temperatures of the DE.
(5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. [P side] - Cable connection - Mode setting switches - Mounting screw hole [Q side] - Mounting screw hole [R side] - Mounting screw hole Figure 3.6 (6) Service area External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.
3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.7 shows the locations of these connectors and terminals. • • Power supply connector (CN1) ATA interface connector (CN1) Power supply connector (CN1) Mode Setting Pins ATA interface connector Figure 3.
3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.
3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). 1 2 3 4 1 +12VDC 2 +12V RETURN 3 +5V RETURN 4 +5VDC (Viewed from cable side) Figure 3.9 3.4 Jumper Settings 3.4.1 Location of setting jumpers Power supply connector pins (CN1) Figure 3.10 shows the location of the jumpers to select drive configuration and functions.
3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. (Master device setting) B02 C01 06 A02 A40 A01 A39 C04 B01 05 Figure 3.11 Factory default setting 3.4.3 Jumper configuration (1) Device type Master device (device #0) or slave device (device #1) is selected. B02 06 B02 06 B01 05 B01 05 (a) Master device (b) Slave device Figure 3.
B02 06 B01 05 CSEL connected to the interface Cable selection can be done by the special interface cable. Figure 3.13 Jumper setting of Cable Select Figures 3.14 and 3.15 show examples of cable selection using unique interface cables. By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and connecting it to ground further, the CSEL is set to low level. The device is identified as a master device. At this time, the CSEL of the slave device does not have a conductor.
(3) Special setting 1 (SP1) The number of cylinders reported by the IDENTIFY DEVICE command is selected. (a) Default mode 2 4 6 1 3 5 Master Device Model 2 4 6 2 1 3 5 Slave Device 4 6 1 3 5 Cable Select No. of cylinders No. of heads No.
CHAPTER 4 THEORY OF DEVICE OPERATION 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write Circuit 4.7 Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks. 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive.
4.2.2 Head Figure 4.1 shows the read/write head structures. The MPB3021AT has 2 read/write heads, the MPB3032AT has 3, MPB3043AT has 4, MPB3052AT has 5, and MPB3064AT has 6. These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed.
4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 5,400 rpm ±0.5%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting. After that, the rotational speed is kept with detecting a servo information. 4.2.4 Actuator The actuator consists of a voice coil motor (VCM) and a head carriage.
4.3 Circuit Configuration Figure 4.2 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC). The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.
Figure 4.
4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor. b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to the ATA bus.
Power on a) Start Self-diagnosis 1 • MPU bus test • Inner register write/read test • Work RAM write/read test The spindle motor starts. b) Self-diagnosis 2 • Data buffer write/read test c) Confirming spindle motor speed Release heads from actuator lock d) Initial on-track and read out of system information e) Execute self-calibration f) Drive ready state (command waiting state) End Figure 4.
4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.
4.5.2 Execution timing of self-calibration Self-calibration is executed when: • • • The power is turned on. The disk drive receives the RECALIBRATE command from the host. The self-calibration execution timechart of the disk drive specifies self-calibration. The disk drive performs self-calibration according to the timechart based on the time elapsed from power-on. The timechart is shown in Table 4.1. After power-on, self-calibration is performed about every 30 minutes. Table 4.
4.6 Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit. 4.6.1 Read/write preamplifier (PreAMP) One PreAMP is mounted on the FPC. The PreAMP consists of an 6-channel read preamplifier and a write current switch and senses a write error. Each channel is connected to each data head.
Figure 4.
4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 8/9 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.
Figure 4.
(4) Viterbi detection circuit The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence. (5) Data separator circuit The data separator circuit generates clocks in synchronization with the output of the adaptive equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the clock signals from a synthesizer.
Table 4.3 Zone Cylinder Transfer rate [MB/s] Zone Cylinder Transfer rate [MB/s] Write clock frequency and transfer rate of each zone 0 1 2 3 4 5 6 7 0 to 660 661 to 1197 1198 to 1938 1939 to 2672 2673 to 3332 3333 to 3958 3959 to 4747 4748 to 5216 16.71 16.35 15.82 15.18 14.68 14.15 13.44 13.06 8 9 10 11 12 13 5217 to 5886 5887 to 6505 6506 to 7073 7074 to 8286 8287 to 8718 8719 to 8982 12.44 11.85 11.33 10.04 9.74 9.
4.7.1 Servo control circuit Figure 4.7 is the block diagram of the servo control circuit. The following describes the functions of the blocks: (1) MPU Head (2) Servo burst capture (3) (4) DSP unit ADC SVC (5) DAC VCM current P. Amp. CSR Position Sense VCM (6) Spindle motor control CSR: Current Sense Resistor VCM: Voice Coil Motor Figure 4.7 (1) (7) Driver Spindle motor Block diagram of servo control circuit Microprocessor unit (MPU) The MPU includes DSP unit, etc.
c. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder. d. Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value. Figure 4.
(2) Servo burst capture circuit The four servo signals can be synchronously detected by the STROB signal, full-wave rectified integrated. (3) A/D converter (ADC) The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and transfers the digital signal to the DSP unit. (4) D/A converter (DAC) The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the DSP unit into analog values and transfers them to the power amplifier.
4.7.2 Data-surface servo format Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.8 are described below. (1) Inner guard band The head is in contact with the disk in this space when the spindle starts turning or stops, and the rotational speed of the spindle can be controlled on this cylinder area for head moving. (2) Data area This area is used as the user data area SA area.
(1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and position-demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit.
d) If the head is stopped at the reference cylinder from there. Track following control starts. (2) Seek operation Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read or instruction is issued, the MPU seeks the desired track. The MPU feeds the VCM current via the D/A converter and power amplifier to move the head.
e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode. (2) Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates.
CHAPTER 5 INTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA feature Set 5.
5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DD(15:0) DATA BUS DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST DIOW-: I/O WRITE DIOR- : I/O READ INTRQ : INTERRUPT REQUEST IOCS16-: IOCS 16 PDIAG- : PASSED DIAGNOSTIC IORDY : I/O CHANNEL READY DASP- : DEVICE ACTIVE/DEVICE 1 PRESENT DA 0-2: DEVICE ADDRESS CS0- : CHIP SELECT 0 CS1- : CHIP SELECT 1 RESET-: RESET CSEL : CABLE SELECT GND: GROUND Figure 5.
5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No.
5-4 [signal] [I/O] [Description] DIOR–, HDMARDY–, HSTROBE I DIOR– is the strobe signal asserted by the host to read device registers or the data port. HDMARDY– is a flow control signal for Ultra DMA data in bursts. This signal is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in bursts. The host may negate HDMARDY- to pause an Ultra DMA data in burst. HSTROBE is the data out strobe signal from the host for an Ultra DMA data out burst.
[signal] [I/O] [Description] IORDY, DDMARDY–, DSTROBE O This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. DDMARDY– is a flow control signal for Ultra DMA data out bursts. This signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts. The device may negate DDMARDY– to pause an Ultra DMA data out burst.
5.2 Logical Interface The device can operate for command execution in either address-specified mode; cylinderhead-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head register indicates the head No.
Table 5.
5.2.2 Command block registers (1) Data register (X'1F0') The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or LBA mode. (2) Error register (X'1F1') The Error register indicates the status of the command executed by the device. The contents of this register are valid when the ERR bit of the Status register is 1.
[Diagnostic code] (3) X'01': No Error Detected. X'03': Data Buffer Compare Error. X'05': ROM Sum Check Error. X'80': Device 1 (slave device) Failed. Error register of the master device is valid under two devices (master and slave) configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic code) with its own status (X'01' to X'05'). However, when the host system selects the slave device, the diagnostic code of the slave device is posted.
(6) Cylinder Low register (X'1F4') The contents of this register indicates low-order 8 bits of the starting cylinder address for any disk-access. At the end of a command, the contents of this register are updated to the current cylinder number. Under the LBA mode, this register indicates LBA bits 15 to 8. (7) Cylinder High register (X'1F5') The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.
(9) Status register (X'1F7') The contents of this register indicate the status of the device. The contents of this register are updated at the completion of each command. When the BSY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt).
(10) - Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device. - Bit 2: Always 0. - Bit 1: Always 0. - Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error. Command register (X'1F7') The Command register contains a command code being sent to the device.
5.2.3 Control block registers (1) Alternate Status register (X'3F6') The Alternate Status register contains the same information as the Status register of the command block register. The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.
5.3.1 Command code and parameters Table 5.3 lists the supported commands, command code and the registers that needed parameters are written. Table 5.
Table 5.
5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) WITH RETRY At command issuance (I/O registers setting contents) Bit 7 6 5 4 3 2 1 0 1F7H(CM) 0 0 1 0 0 0 0 0 1F6H(DH) × L × DV Head No.
Note: (1) 1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). 2. At error occurrence, the SC register indicates the remaining sector count of data transfer. 3. In the table indicating I/O registers contents in this subsection, bit indication is omitted.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Status information × L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
Figure 5.2 shows an example of the execution of the READ MULTIPLE command. • • Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a block) READ MULTIPLE command specifies; Number of requested sectors = 9 (Sector Count register = 9) ↓ Number of sectors in incomplete block = remainder of 9/4 =1 Command Issue Parameter Write Status read ~ Status read Status read BSY DRDY INTRQ DRQ 1 Sector transferred 2 3 5 4 Block Figure 5.
Note: If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register. (3) READ DMA (X'C8' or X'C9') This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Status information × L × DV End head No. /LBA [MSB] End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
The contents of the command block registers related to addresses after the transfer of a data block containing an erred sector are undefined. To obtain a valid error information, the host should retry data transfer as an individual requests. At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) × L × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 1 0 1 Start head No. /LBA [MSB] Start cylinder No. [MSB]/ LBA Start cylinder No. [LSB] / LBA Start sector No.
1) Single word DMA transfer mode 2: Sets the FR register = X'03' and SC register command = X'12' by the SET FEATURES 2) Multiword DMA transfer mode 2: Sets the FR register = X'03' and SC register command = X'22' by the SET FEATURES 3) Ultra DMA transfer mode 2: Sets the FR register = X'03' and SC register command = X'42' by the SET FEATURES At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) × L × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 0 1 R Start h
At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 1 1 1F6H(DH) × L × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 1 0 0 Start head No. /LBA [MSB] Start cylinder No. [MSB]/ LBA Start cylinder No. [LSB] / LBA Start sector No. / LBA [LSB] Transfer sector count xx R = 0 →with Retry R = 1 →without Retry At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) L × DV End head No.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (10) DV xx xx xx xx xx Error information SEEK (X'7x', x : X'0' to X'F') This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt.
(11) INITIALIZE DEVICE PARAMETERS (X'91') The host system can set the number of sectors per track and the maximum head number (maximum head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt. When the SC register is specified to X'00', an ABORTED COMMAND error is posted.
At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 1 0 0 xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Status information × × × DV xx xx xx xx xx Error information C141-E045-02EN 5 - 29
Table 5.
Table 5.
Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3) *8 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command Bit 15-9: Reserved Bit 8: Multiple sector transfer 1=Enable Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without interrupt supports 2, 4, 8, 16 and 32 sectors.
(13) IDENTIFY DEVICE DMA (X'EE') When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.
Table 5.5 Features register values and settable modes Features Register Drive operation mode X‘02’ Enables the write cache function. X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2, and multiword DMA mode regardless of Sector Count register contents. X‘55’ Disables read cache function. X‘66’ Disables the reverting to power-on default settings after software reset. X‘82’ Disables the write cache function. X‘AA’ Enables the read cache function.
The host sets X'03' to the Features register. By issuing this command with setting a value to the Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value. However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting.
At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 1 1 0 xx xx xx xx Sector count/block xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Status information × × × DV xx xx xx xx Sector count/block Error information After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the
(16) EXECUTE DEVICE DIAGNOSTIC (X'90') This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis. If device 1 is present: • • • • • Both devices shall execute self-diagnosis. The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal.
At command issuance (I/O registers setting contents) 1F7H(CM) 1 0 0 1 1F6H(DH) × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 0 0 0 xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × DV xx xx xx 01H (*1) 01H Diagnostic code *1 This register indicates X‘00’ in the LBA mode.
At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 1 0 1F6H(DH) × L × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 0 1 R Head No. /LBA [MSB] Cylinder No. [MSB] / LBA Cylinder No. [LSB] / LBA Sector No. / LBA [LSB] Number of sectors to be transferred xx R = 0 →with Retry R = 1 →without Retry At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) Status information × × L DV Head No.
At command issuance (I/O registers setting contents) 1F7H(CM) 0 0 1 1 1F6H(DH) × L × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 0 0 1 R Head No. /LBA [MSB] Cylinder No. [MSB] / LBA Cylinder No. [LSB] / LBA Sector No. / LBA [LSB] Number of sectors to be transferred xx R = 0 →with Retry R = 1 →without Retry At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × L 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × DV Head No.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (21) DV xx xx xx xx xx Error information WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register.
(22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (23) xx xx xx xx xx Error information IDLE IMMEDIATE (X'95' or X'E1') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic power-down function.
(24) STANDBY (X'96' or X'E2') Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode. If the device has already spun down, the spin-down sequence is not implemented.
At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) X'94' or X'E0' × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (26) DV xx xx xx xx xx Error information SLEEP (X'99' or X'E6') This command is the only way to make the device enter the sleep mode.
At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) Status information × × × 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (27) DV xx xx xx xx xx Error information CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers. The device sets the BSY bit and sets the following register value.
At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) X'98' or X'E5' × × × DV 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) xx xx xx xx xx xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (28) Status information × × × DV xx xx xx xx X'00' or X'FF' Error information SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register.
Table 5.7 Features Register values (subcommands) and functions Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512byte attribute value information to the host. * For information about the format of the attribute value information, see Table 5.8.
The host can predict failures in the device by periodically issuing the SMART Return Status subcommand (FR register = DAh) to reference the CL and CH registers. If an attribute value is below the insurance failure threshold value, the device is about to fail or the device is nearing the end of it life . In this case, the host recommends that the user quickly backs up the data.
The attribute value information is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Values subcommand (FR register = D0h). The insurance failure threshold value data is 512-byte data; the format of this data is shown below. The host can access this data using the SMART Read Attribute Thresholds subcommand (FR register = D1h). Table 5.
Table 5.9 Format of insurance failure threshold value data Byte Item 00 01 Data format version number 02 Attribute 1 03 04 Attribute ID Insurance failure threshold Threshold 1 (Threshold of attribute 1) Reserved to 0D 0E to 169 16A Threshold 2 to threshold 30 (The format of each threshold value is the same as that of bytes 02 to 0D.
• Attribute ID The attribute ID is defined as follows: Attribute ID 0 (Indicates unused attribute data.
• Raw attribute value Raw attributes data is retained. • Failure prediction capability flag Bit 0: The attribute value data is saved to a medium before the device enters power saving mode. Bit 1: The device automatically saves the attribute value data to a medium after the previously set operation. Bits 2 to 15: Reserved bits • Check sum Two's complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning.
(29) FLUSH CACHE (X ‘E7’) This command is use by the host to request the device to flush the write cache. If the write cache is to be flushed, all data cached shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. The device should use all error recovery methods available to ensure the data is written successfully.
5.3.3 Error posting Table 5.10 lists the defined errors that are valid for each command. Table 5.
5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1. However, the following commands can be executed even if DRDY bit is 0. • • 5.4.
Command Parameter write ~ Status read a BSY Status read b c •••• e d DRDY f e d •••• DRQ INTRQ Data transfer Expanded Command Min. 30 µs (*1) ••• DRQ INTRQ Data Reg. Selection Data •••• •••• IOR- •••• Word 0 1 2 255 IOCS16*1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from the buffer without reading from the disk medium. Figure 5.
Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 µs after the completion of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.
c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and clears BSY bit. d) The host writes one sector of data through the Data register. e) The device clears the DRQ bit and sets the BSY bit. f) When the drive completes transferring the data of the sector, the device clears BSY bit and asserts INTRQ signal. If transfer of another sector is requested, the drive sets the DRQ bit. g) After detecting the INTRQ signal assertion, the host reads the Status register.
Note: For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to 50 µs after the completion of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.
5.4.4 Other commands • • • READ MULTIPLE SLEEP WRITE MULTIPLE See the description of each command. 5.4.5 DMA data transfer commands • • READ DMA WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance. The interrupt processing for the DMA transfer differs the following point. • The interrupt processing for the DMA transfer differs the following point.
Parameter write Command Status read ~ •• BSY DRDY INTRQ •• DRQ •• Data transfer Expanded [Single Word DMA transfer] •••• DRQ •••• DMARQ DMACK- •••• •••• IOR- or IOWWord 0 2 1 [Multiword DMA transfer] 255 •••• DRQ •••• DMARQ DMACK- •••• •••• IOR- or IOWWord 0 Figure 5.
5.5 Ultra DMA feature set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).
5.5.2 Phases of operation An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for each of these phases, 5.6.4 defines the specific timing requirements).
11) The device shall drive the first word of the data transfer onto DD (15:0). This step may occur when the device first drives DD (15:0) in step (10). 12) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no sooner than tDVS after driving the first word of data onto DD (15:0). 5.5.3.
3) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY-. 4) If the host negates HDMARDY- within tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words.
10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of DMACK-. 11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command the device shall report the first error that occurred (see 5.5.5). 12) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.
10) If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5). 11) The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated HDMARDY-, and no sooner than tDVS after the host places the result of its CRC calculation on DD (15:0).
9) The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host. 10) The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation. 11) To transfer the first word of data: the host shall negate HSTROBE no sooner than tLI after the device has asserted DDMARDY-.
b) Device pausing an Ultra DMA data out burst 1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred. 2) The device shall pause an Ultra DMA burst by negating DDMARDY-. 3) The host shall stop generating HSTROBE edges within tRFS of the device negating DDMARDY-. 4) If the device negates DDMARDY- within tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words.
9) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5). 10) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-. 11) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating DMACK-.
11) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5). 12) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-. 13) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-.
I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is shifted in first and DD15 is shifted in last. 5.5.
5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system.
t0 Addresses t1 t9 t2 DIOR-/DIOW- t2i Write data DD0-DD15 t3 t4 Read data DD0-DD15 t5 t6 t8 IOCS16t7 t10 IORDY t11 t12 Symbol Timing parameter Min. Max.
5.6.2 Single word DMA data transfer Figure 5.10 show the single word DMA data transfer timing between the device and the host system. t0 DMARQ DMACK- tC tI tJ tD DIOR-/DIOW- Write data DD0-DD15 tG tH Read data DD0-DD15 tE Symbol Timing parameter tF Min. Max.
5.6.3 Multiword data transfer Figure 5.11 shows the multiword DMA data transfer timing between the device and the host system. t0 DMARQ DMACK- tJ tC tI tK tD DIOR-/DIOW- Write data DD0-DD15 tG tH Read data DD0-DD15 tE Symbol Timing parameter tF Min. Max.
5.6.4 Ultra DMA data transfer Figures 5.12 through 5.21 define the timings associated with all phases of Ultra DMA bursts. Table 5.12 contains the values for the timings for each of the Ultra DMA Modes. 5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY-and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.
5.6.4.2 Ultra DMA data burst timing requirements Table 5.
Table 5.
5.6.4.3 Sustained Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 5.
5.6.4.4 Host pausing an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY- is negated. 2) If the tSR timing is not satisfied, the host may receive zero, one or two more data words from the device. Figure 5.
5.6.4.5 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.
5.6.4.6 Host terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.
5.6.4.7 Initiating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted. Figure 5.
5.6.4.8 Sustained Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. Figure 5.
5.6.4.9 Device pausing an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY- is negated. 2) If the tSR timing is not satisfied, the device may receive zero, one or two more data words from the host. Figure 5.
5.6.4.10 Host terminating an Ultra DMA data out burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.
5.6.4.11 Device terminating an Ultra DMA data in burst 5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes. Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 5.
5.6.5 Power-on and reset Figure 5.22 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESETSoftware reset tM tN BSY DASPtP *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device] tN BSY DASP[Slave device] BSY tQ tP PDIAG- tS DASPtR Symbol Timing parameter Min. Max.
CHAPTER 6 6.1 OPERATIONS 6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command.
6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1). The master device recognizes presence of the slave device when it confirms assertion of the DASP- signal. Then, the master device checks a PDIAG- signal to see if the slave device has successfully completed the power-on diagnostics.
6.1.2 Response to hardware reset Response to RESET- (hardware reset through the interface) is similar to the power-on reset. Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to confirm presence of a slave device. The master device recognizes the presence of the slave device when it confirms assertion of the DASP- signal. Then the master device checks a PDIAG- signal to see if the slave device has successfully completed the self-diagnostics.
6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave device has completed the self-diagnosis successfully.
6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self-diagnosis successfully. The master device does not check the DASP- signal.
6.2 Address Translation When the IDD receives any command which involves access to the disk medium, the IDD always implements the address translation from the logical address (a host-specified address) to the physical address (logical to physical address translation). Following subsections explains the CHS translation mode. 6.2.
6.2.2 Logical address (1) CHS mode Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is specified by the INITIALIZE DEVICE PARAMETERS command. The head address is advanced at the subsequent sector from the last sector of the current physical head address.
(2) LBA mode Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, and physical sector 1. The logical address is advanced at the subsequent sector from the last sector of the current track. The first physical sector of the subsequent physical track is the consecutive logical sector from the last sector of the current physical track. Figure 6.6 shows an example of (assuming there is no track skew).
Regardless of whether the power down is enabled, the device enters the idle mode. The device also enters the idle mode in the same way after power-on sequence is completed. (1) Active mode In this mode, all the electric circuit in the device are active or the device is under seek, read or write operation. A device enters the active mode under the following conditions: (2) • Power-on sequence is completed. • A command other than power commands is issued.
(4) • STANDBY command • STANDBY IMMEDIATE command • INITIALIZE DEVICE PARAMETERS command • CHECK POWER MODE command Sleep mode The power consumption of the drive is minimal in this mode. The drive enters only the standby mode from the sleep mode. The only method to return from the standby mode is to execute a software or hardware reset. The drive enters the sleep mode under the following condition: • A SLEEP command is issued. Issued commands are invalid (ignored) in this mode. 6.3.
6.4.1 Spare area Following two types of spare area are provided for every physical head. 1) Spare cylinder for sector slip: used for alternating defective sectors at formatting in shipment (11 cylinders/head) 2) Spare cylinder for alternative assignment: used for alternative assignment by automatic alternative assignment. (4 cylinders/head) 6.4.
(2) Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder. This processing is performed when the automatic alternate processing is performed. Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0.
(3) Automatic alternate assignment The device performs the automatic assignment at following case. 1) When ECC correction performance is increased during read error retry, a read error is recovered. Before automatic alternate assignment, the device performs rewriting the corrected data to the erred sector and rereading. If no error occurs at rereading, the automatic alternate assignment is not performed. 2) When a write error occurs and the error does not recovered. 6.
6.5.2 Caching operation Caching operation is performed only at issuance of the following commands. The device transfers data from the data buffer to the host system at issuance of following command if following data exist in the data buffer. • • All sectors to be processed by the command A part of data including load sector to be processed by the command When a part of data to be processed exist in the data buffer, remaining data are read from the medium and are transferred to the host system.
(3) Invalidating caching data Caching data in the data buffer is invalidated in the following case. 1) Following command is issued to the same data block as caching data. • WRITE SECTOR(S) • WRITE DMA • WRITE MULTIPLE 2) Command other than following commands is issued (all caching data are invalidated) • READ SECTOR (S) • READ DMA • READ MULTIPLE • WRITE SECTOR(S) • WRITE MULTIPLE • WRITE DMA 3) Caching operation is inhibited by the SET FEATURES command. 4) Issued command is terminated with an error.
1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the lead of segment. HAP Segment only for read DAP 2) Transfers the requested data that already read to the host system with reading the requested data from the disk media.
(3) Sequential read When the disk drive receives the read command that targets the sequential address to the previous read command, the disk drive starts the read-ahead operation. a.
4) The disk drive performs the read-ahead operation for all area of segment with overwriting the requested data. Finally, the cache data in the buffer is as follows. HAP Read-ahead data DAP Last LBA Start LBA b. Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command, the disk drive transfers the hit data in the buffer to the host system.
3) After completion of data transfer of hit data, the disk drive performs the read-ahead operation for the data area of which the disk drive transferred hit data. HAP Read-ahead data DAP 4) Finally, the cache data in the buffer is as follows. Read-ahead data Start LBA Last LBA c.
1) In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command, the disk drive sets the HAP to the address of which the hit data is stored. Last position at previous read command HAP (set to hit position for data transfer) HAP Cache data Full hit data Cache data DAP Last position at previous read command 2) The disk drive transfers the requested data but does not perform the read-ahead operation.
1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets the DAP to the address just after the partially hit data. HAP Partially hit data Lack data DAP 2) The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time. However, the disk drive does not perform the read-ahead operation newly.
6.6 Write Cache The write cache function of the drive makes a high speed processing in the case that data to be written by a write command is logically sequent the data of previous command and random write operation is performed. When the drive receives a write command, the drive starts transferring data of sectors requested by the host system and writing on the disk medium. After transferring data of sectors requested by the host system, the drive generates the interrupt of command complete.
At the time that the drive has stopped the command execution after the error recovery has failed, the write cache function is disabled automatically. The releasing the disable state can be done by the SET FEATURES command. When the power of the drive is turned on after the power is turned off once, the status of the write cache function returns to the default state. The default state is “write cache enable”, and can be disable by the SET FEATURES command.
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