Recording Equipment User Manual

ManualsBrandsFujitsu ManualsRecording EquipmentMB15F74UV

DS04-21381-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

Dual S

erial Input

PLL Frequency

Synthesizer

MB15F74UV

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DESCRIPTION

The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and

a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the

2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range

is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA

selectable by serial date. The serial data format is the same as MB15F74UL. Fast locking is achieved for adopting

the new circuit.

MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50% com-

paring with the former BCC20 (for dual PLL) .

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FEATURES

• High frequency operation : RF synthesizer : 4000 MHz Max

: IF synthesizer : 2000 MHz Max

• Low power supply voltage : VCC = 2.7 V to 3.6 V

• Ultra low power supply current : I

CC = 9.0 mA Typ

(VCC = 3.0 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)

(Continued)

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PACKAGE

18-pin plastic BCC

(LCC-18P-M05)

Summary of content (25 pages)

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FUJITSU SEMICONDUCTOR DATA SHEET DS04-21381-1E ASSP Dual Serial Input PLL Frequency Synthesizer MB15F74UV ■ DESCRIPTION The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V.
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MB15F74UV (Continued) • Direct power saving function : Power supply current in power saving mode Typ 0.1 µA (VCC = 3.0 V, Ta = +25 °C at 1 system) Max 10 µA (VCC = 3.0 V at 1 system) • Software selectable charge pump current : 1.5 mA/6.
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MB15F74UV ■ PIN DESCRIPTION Pin no. Pin name I/O 1 GND  2 finIF I Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. 3 XfinIF I Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. 4 GNDIF  Ground pin for the IF-PLL section. 5 VCCIF  Power supply voltage input pin for the IF-PLL section, the shift register and the oscillator input buffer. 6 DoIF O Charge pump output for the IF-PLL section.
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MB15F74UV ■ BLOCK DIAGRAM VCCIF GNDIF (4) (5) Intermittent mode control (IF-PLL) FCIF SWIF 3 bit latch LDS PSIF (7) 7 bit latch 11 bit latch Binary 7-bit Binary 11-bit swallow counter programmable (IF-PLL) counter (IF-PLL) Charge Current pump Switch (IF-PLL) Phase Fast comp. lock (IF-PLL) Tuning (6) DoIF fpIF finIF (2) XfinIF (3) Prescaler (IF-PLL) (32/33, 64/65) Lock Det. (IF-PLL) 2 bit latch T1 T2 14 bit latch 1 bit latch Binary 14-bit programmable ref.
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MB15F74UV ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Unit Min Max VCC −0.5 4.0 V VI −0.5 VCC + 0.5 V LD/fout VO GND VCC V DoIF, DoRF VDO GND VCC V Tstg −55 +125 °C Power supply voltage Input voltage Output voltage Rating Storage temperature WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB15F74UV ■ ELECTRICAL CHARACTERISTICS * (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol Input sensitivity “L” level input voltage “H” level input voltage “L” level input voltage “H” level input current “L” level input current Typ Max Unit finIF = 2000 MHz VCCIF = 3.0 V 2.1 2.5 3.2 mA ICCRF *1 finRF = 2500 MHz VCCRF = 3.0 V 5.7 6.5 8.4 mA IPSIF PSIF = PSRF = “L”  0.1 *2 10 µA IPSRF PSIF = PSRF = “L”  0.
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MB15F74UV (Continued) (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C) Parameter Symbol IDOL/IDOH IDOMT *5 Charge pump current rate DOVD 6 vs VDO I vs Ta IDOTA *7 * Value Condition Unit Min Typ Max VDO = VCC / 2  3 10 % 0.5 V ≤ VDO ≤ VCC − 0.5 V  10 15 % −40 °C ≤ Ta ≤ 85 °C, VDO = VCC / 2  5 10 % *1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “0” in locking state. *2 : VCCIF = VCCRF = 3.0 V, fosc = 12.8 MHz, Ta = +25 °C, in power saving mode.
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MB15F74UV ■ FUNCTIONAL DESCRIPTION 1.
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MB15F74UV • Programmable Counter (LSB) 1 2 Data Flow 3 4 5 SWIF/ SWRF CN1 CN2 LDS A1 to A7 N1 to N11 LDS SWIF/SWRF FCIF/FCRF CN1, CN2 6 7 8 (MSB) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 FCIF/ A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 FCRF : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bits for the programmable counter (3 to 2,047) : LD/fout signal select bit : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF) : Phase co
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MB15F74UV • Prescaler Data Setting SW = “1” SW = “0” Prescaler divide ratio IF-PLL 32/33 64/65 Prescaler divide ratio RF-PLL 64/65 128/129 Divide ratio • Charge Pump Current Setting Current value CS ±6.0 mA 1 ±1.
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MB15F74UV 3. Power Saving Mode (Intermittent Mode Control Circuit) Status PS pin Normal mode H Power saving mode L The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
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MB15F74UV 4. Serial Data Data Input Timing Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing.
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MB15F74UV ■ PHASE COMPARATOR OUTPUT WAVEFORM fr IF/RF fp IF/RF t WU t WL LD (FC bit = “1”) D o IF/RF H Z L (FC bit = “0”) H D o IF/RF Z L • LD Output Logic IF-PLL section RF-PLL section LD output Locking state/Power saving state Locking state/Power saving state H Locking state/Power saving state Unlocking state L Unlocking state Locking state/Power saving state L Unlocking state Unlocking state L Notes : • Phase error detection range = −2π to +2π • Pulses on DoIF/RF signals during l
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MB15F74UV ■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) S.G. 1000 pF 50 Ω S.G. 1000 pF Controller (divide ratio setting) 50 Ω OSCIN Clock Data LE GND S.G. 1 18 17 16 15 1000 pF finIF 50 Ω XfinIF 2 14 3 13 1000 pF MB15F74UV 4 12 5 11 GNDIF DoIF finRF 0.1 µF 1000 pF XfinRF GNDRF VCCRF VCCIF VCCIF VCCRF 6 7 PSIF 8 9 LD/ fout 10 DoRF PSRF 0.
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MB15F74UV ■ TYPICAL CHARACTERISTICS 1. fin input sensitivity RF-PLL input sensitivity vs. Input frequency Ta = +25 C 10 PfinRF [dBm] 0 VCC = 2.7 V Catalog guaranteed range −10 VCC = 3.0 V −20 VCC = 3.6 V −30 SPEC −40 −50 1500 2000 2500 3000 3500 4000 4500 5000 finRF [MHz] IF-PLL input sensitivity vs. Input frequency 10 Ta = +25 C PfinIF [dBm] 0 VCC = 2.7 V Catalog guaranteed range −10 VCC = 3.0 V VCC = 3.
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MB15F74UV 2. OSCIN input sensitivity Input sensitivity vs. Input frequency Input sensitivity VOSC (dBm) 10 Catalog guaranteed range 0 VCC = 2.7 V −10 VCC = 3.0 V VCC = 3.
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MB15F74UV 3. RF/IF-PLL Do output current • 1.5 mA mode IDO − VDO Charge pump output current IDO (mA) 2.50 VCC = 2.7 V, Ta = +25 C 2.00 1.50 1.00 0.50 0.00 −0.50 −1.00 −1.50 −2.00 −2.50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Charge pump output voltage VDO (V) • 6.0 mA mode IDO − VDO Charge pump output current IDO (mA) 8.00 VCC = 2.7 V, Ta = +25 C 6.00 4.00 2.00 0.00 −2.00 −4.00 −6.00 −8.00 0.0 0.5 1.0 1.5 2.0 2.5 3.
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MB15F74UV 4. fin input impedance finIF input impedance 4 : 30.266 Ω −102.92 Ω 773.21 fF 2 000.000 000 MHz 1 : 494.28 Ω −874.84 Ω 200 MHz 2 : 58.094 Ω −216.47 Ω 1 GHz 3 : 39.773 Ω −148 Ω 1.5 GHz 1 2 4 3 START 100.000 000 MHz STOP 2 000.000 000 MHz finRF input impedance 4 : 20.93 Ω −39.352 Ω 1.0111 pF 4 000.000 000 MHz 4 1 3 START 2 000.000 000 MHz 18 2 STOP 4 000.000 000 MHz 1: 37.563 Ω −109.96 Ω 2 GHz 2: 26.125 Ω −71.227 Ω 3 GHz 3: 22.848 Ω −54.025 Ω 3.
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MB15F74UV 5. OSCIN input impedance OSCIN input impedance 4 : 278.69 Ω −1.0537 kΩ 3.7761 pF 40.000 000 MHz 1 : 2.25 kΩ −2.2373 kΩ 10 MHz 2 : 881.62 Ω −1.8299 kΩ 20 MHz 4 3 : 448.75 Ω −1.353 kΩ 30 MHz 21 3 START 3.000 000 MHz STOP 40.
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MB15F74UV ■ REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage) Test Circuit S.G. OSCIN Do LPF fVCO = 2113.6 MHz VCC = 3.0 V KV = 50 MHz/V Ta = + 25 °C fr = 50 kHz CP : 6 mA mode fOSC = 19.2 MHz LPF fin 7.5 kΩ Spectrum Analyzer VCO To VCO 0.01 F 1.6 kΩ 3300 pF 0.1 F • PLL Reference Leakage ATTEN 10 dB RL 0 dBm VAVG 16 10 dB/ ∆MKR −80.83 dB 50.0 kHz ∆MKR 50.0 kHz −80.83 dB CENTER 2.1136000 GHz ∗ RBW 1.0 kHz VBW 1.0 kHz SPAN 200.
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MB15F74UV (Continued) PLL Lock Up time 2113.6 MHz→2173.6 MHz within ± 1 kHz L ch→H ch 1.47 ms A Mkr x: 439.99764 µs y: 50.0009 MHz 2.173604000 GHz 2.173600000 GHz 2.173596000 GHz -500 µs 2.000 ms 4.500 ms 500 µs/div PLL Lock Up time 2173.6 MHz→2113.6 MHz within ± 1 kHz H ch→L ch 1.56 ms A Mkr x: 400.00146 µs y: −50.0013 MHz 2.113604000 GHz 2.113600000 GHz 2.113596000 GHz -500 µs 2.000 ms 4.
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MB15F74UV ■ APPLICATION EXAMPLE 1000 pF Controller (divide ratio setting) TCXO OSCIN Clock Data LE OUTPUT OUTPUT GND 1 18 17 16 15 1000 pF finIF XfinIF 2 14 3 13 1000 pF VCO MB15F74UV 4 12 5 11 GNDIF finRF XfinRF 1000 pF 1000 pF GNDRF VCCRF LPF VCCIF VCCRF 6 VCCIF 7 8 9 VCO LPF 0.1 µF 10 DoRF DoIF PSIF LD/ fout PSRF 0.
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MB15F74UV ■ USAGE PRECAUTIONS (1) VCCRF and VCCIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF and VCCIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : • Store and transport devices in conductive containers. • Use properly grounded workstations, tools, and equipment.
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MB15F74UV ■ PACKAGE DIMENSION 18-pin plastic BCC (LCC-18P-M05) 15 2.70±0.10 (.106±.004) INDEX AREA 0.45±0.05 (.018±.002) (Mount height) 10 10 2.01(.079) TYP 2.40±0.10 (.094±.004) 0.45(.018) TYP. 1 0.075±0.025 (.003±.001) (Stand off) 6 2.31(.090) TYP 0.45(.018) TYP. 0.90(.035) REF 1.90(.075) REF "A" "B" "C" 6 15 1.35(.053) REF 1 2.28(.090) REF Details of "A" part 0.05(.002) 0.14(.006) MIN. Details of "B" part 0.25±0.06 (.010±.002) 0.25±0.06 (.010±.002) C C0.10(.
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MB15F74UV FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.