Dual-Core Intel® Xeon® Processor 5100 Series Datasheet August 2007 Reference Number: 313355-003
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Contents Features...................................................................................................................... 9 1 Introduction............................................................................................................... 11 1.1 Terminology ..................................................................................................... 12 1.2 State of Data ....................................................................................................
6.3 6.2.2 On-Demand Mode ...................................................................................84 6.2.3 PROCHOT# Signal ..................................................................................85 6.2.4 FORCEPR# Signal ...................................................................................85 6.2.5 THERMTRIP# Signal ................................................................................86 Platform Environment Control Interface (PECI) ................................
6-2 Dual-Core Intel® Xeon® Processor LV 5138 Nominal & Short-Term Thermal Profiles ................................................................ 77 6-3 Dual-Core Intel® Xeon® Processor LV 5148 and Dual-Core Intel® Xeon® Processor LV 5128 Thermal Profile ................................... 79 6-4 Dual-Core Intel® Xeon® Processor 5160 Thermal Profiles A and B .......................... 80 6-5 Case Temperature (TCASE) Measurement Location ................................................
-1 6-2 6-3 6-4 6-5 6-6 Dual-Core Intel® Xeon® Processor 5100 Series Thermal Specifications ....................75 Dual-Core Intel® Xeon® Processor 5100 Series Thermal Profile Table........................76 Dual-Core Intel® Xeon® Processor LV 5138 Thermal Specifications .........................77 Dual-Core Intel® Xeon® Processor LV 5138 Nominal Thermal Profile Table ...............78 Dual-Core Intel® Xeon® Processor LV 5138 Short Term Thermal Profile Table...........
Revision History Revision Description Date 001 Initial release 002 Updated Sections 2, 3, and 6 with SKUs for 5148/5138/5128 June 2006 003 Updated Sections 2, 3, and 6 with G-step information.
Dual-Core Intel® Xeon® Processor 5100 Series Datasheet
Features Features • Dual-Core processing with Intel® Core™ microarchitecture • FC-LGA6 package with 771 Lands • Available at up to 3.
Features 10 Dual-Core Intel® Xeon® Processor 5100 Series Datasheet
Introduction 1 Introduction The Dual-Core Intel® Xeon® Processor 5100 Series are 64-bit server/workstation processors utilizing two Intel microarchitecture cores. These processors are based on Intel’s 65 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Dual-Core Intel® Xeon® Processor 5100 Series maintain the tradition of compatibility with IA-32 software.
Introduction Monitor software enabling multiple, independent software environments inside a single platform. Further details on Intel Virtualization Technology can be found at http:// developer.intel.com/technology/vt. The Dual-Core Intel® Xeon® Processor 5100 Series are intended for high performance server and workstation systems. The Dual-Core Intel® Xeon® Processor 5100 Series support a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets in a system.
Introduction • Dual-Core Intel® Xeon® Processor 5100 Series – Intel 64-bit microprocessor intended for dual processor servers and workstations. The Dual-Core Intel® Xeon® Processor 5100 Series are based on Intel’s 65 nanometer process, in the FC-LGA6 package with two processor cores. For this document, “processor” is used as the generic term for the Dual-Core Intel® Xeon® Processor 5100 Series.
Introduction • Priority Agent – The priority agent is the host bridge to the processor and is typically known as the chipset. • Symmetric Agent – A symmetric agent is a processor which shares the same I/O subsystem and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems.
Introduction Document AP-485, Intel ® Intel Order Number Processor Identification and the CPUID Instruction 241618 Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture 253665 253666 253667 253668 253669 Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z Intel® 64 and IA-32 Architectures Softwa
Introduction 16 Dual-Core Intel® Xeon® Processor 5100 Series Datasheet
Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel® Xeon® Processor 5100 Series FSB signals uses Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination.
Electrical Specifications 2.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the Dual-Core Intel® Xeon® Processor 5100 Series are capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Electrical Specifications The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the CLOCK_FLEX_MAX MSR. For details of operation at core frequencies lower than the maximum rated processor speed, refer to the Conroe and Woodcrest Processor Family BIOS Writer’s Guide.
Electrical Specifications Table 2-2. 2.4.2 BSEL[2:0] Frequency Table (Sheet 2 of 2) BSEL2 BSEL1 BSEL0 Bus Clock Frequency 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved PLL Power Supply An on-die PLL filter solution is implemented on the Dual-Core Intel® Xeon® Processor 5100 Series. The VCCPLL input is used for this configuration in Dual-Core Intel® Xeon® Processor 5100 Series based platforms. Please refer to Table 2-13 for DC specifications.
Electrical Specifications Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable. Table 2-3. VID6 400 mV VID5 200 mV Voltage Identification Definition VID4 100 mV VID2 VID1 50 mV 25 mV 12.5 mV VCC_MAX VID3 VID6 400 mV VID5 200 mV VID4 100 mV VID2 VID1 50 mV 25 mV 12.5 mV VCC_MAX VID3 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.
Electrical Specifications Table 2-4. HEX VID6 400 mV Voltage Identification Definition VID5 200 mV VID4 100 mV VID3 50 mV VID2 VID1 12.5 mV VCC_MAX HEX 25 mV VID6 VID5 VID4 VID3 VID2 VID1 12.5 mV VCC_MAX 400 mV 200 mV 100 mV 50 mV 25 mV 7A 1 1 1 1 0 1 0.8500 3C 0 1 1 1 1 0 1.2375 78 1 1 1 1 0 0 0.8625 3A 0 1 1 1 0 1 1.2500 76 1 1 1 0 1 1 0.8750 38 0 1 1 1 0 0 1.2625 74 1 1 1 0 1 0 0.8875 36 0 1 1 0 1 1 1.
Electrical Specifications Table 2-5. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 LL_ID0 0 0 Reserved 0 1 Dual-Core Intel® Xeon® Processor 5100 Series 1 0 Reserved 1 1 Reserved Note: Table 2-6. The LL_ID[1:0] signals are used to select the correct loadline slope for the processor. Market Segment Selection Truth Table for MS_ID[1:0] MS_ID1 MS_ID0 0 0 Reserved 0 1 Dual-Core Intel® Xeon® Processor 5100 Series 1 0 Reserved 1 1 Reserved Note: 2.
Electrical Specifications 2.7 Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF_DATA and GTLREF_ADD as reference levels. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
Electrical Specifications Notes: 1. Refer to Section 5 for signal descriptions. 2. These signals may be driven simultaneously by multiple agents (Wired-OR). Table 2-9 outlines the signals which include on-die termination (RTT). Table 2-9 outlines non AGTL+ signals including open drain signals. Table 2-10 provides signal reference voltages. Table 2-8.
Electrical Specifications accepting an input of the appropriate voltage. Similar considerations must be made for TCK, TMS, TDO, and TRST#. Two copies of each signal may be required with each driving a different voltage level. 2.10 Platform Environmental Control Interface (PECI) DC Specifications The release of the Dual-Core Intel® Xeon® Processor 5100 Series marks the transition from thermal diodes to digital thermal sensors for fan speed control.
Electrical Specifications 2.10.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-1 as a guide for input buffer design. Figure 2-1. Input Device Hysteresis VTT Maximum VP PECI High Range Minimum VP Minimum Hysteresis Valid Input Signal Range Maximum VN Minimum VN PECI Low Range PECI Ground 2.
Electrical Specifications At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded.
Electrical Specifications 2.13 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 4-1 for the Dual-Core Intel® Xeon® Processor 5100 Series land listings and Section 5.1 for signal definitions. Voltage and current specifications are detailed in Table 2-13. For platform planning refer to Table 2-14, which provides VCC static and transient tolerances.
Electrical Specifications Table 2-13. Voltage and Current Specifications (Sheet 2 of 2) Symbol Min Typ Notes Max Unit ICC for VTT supply before VCC stable ICC for VTT supply after VCC stable 4.
Electrical Specifications 14. ICC_TDC is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for further details. The processor is capable of drawing ICC_TDC indefinitely.
Electrical Specifications 2. Figure 2-4. Not 100% tested. Specified by design characterization. Dual-Core Intel® Xeon® Processor 5160 Load Current versus Time 95 Sustained Current (A) 90 85 80 75 70 65 0.01 0.1 1 10 100 1000 Time Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Table 2-14.
Electrical Specifications 4. Figure 2-5. The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 11.
Electrical Specifications Figure 2-6. Dual-Core Intel® Xeon® Processor LV 5148/5138/5128 VCC Static and Transient Tolerance Load Lines Icc [A] 0 10 20 30 40 VID - 0.000 Vcc Maximum VID - 0.020 Vcc [V] VID - 0.040 VID - 0.060 Vcc Minimum Vcc Typical VID - 0.080 VID - 0.100 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.13.1 for VCC overshoot specifications. 2. Refer to Table 2-13 for processor VID information. 3.
Electrical Specifications Table 2-16. CMOS Signal Group and TAP Signal Group DC Specifications Symbol Parameter Min VOH Output High Voltage IOL Output Low Current IOH ILI Units Notes1 VTT+0.1 V 2 4.70 mA 4 N/A 4.70 mA 5 N/A ± 100 μA 6 Typ Max 0.9*VTT VTT 1.70 N/A Output High Current 1.70 Input Leakage Current N/A Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Electrical Specifications Figure 2-7. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.13.
Mechanical Specifications 3 Mechanical Specifications The Dual-Core Intel® Xeon® Processor 5100 Series is packaged in a Flip Chip Land Grid Array (FC-LGA6) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.
Mechanical Specifications Figure 3-2. Processor Package Drawing (Sheet 1 of 3) Note: 38 Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines.
Mechanical Specifications Figure 3-3.
Mechanical Specifications Figure 3-4.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or landside of the package substrate. See Figure 3-4 for keepout zones. 3.
Mechanical Specifications 9. 3.4 Refer to the Dual-Core Intel® Xeon® Processor 5100 SeriesThermal/Mechanical Design Guidelines or DualCore Intel® Xeon® Processor LV 5138 in Embedded Applications Thermal/Mechanical Design Guidelines for information on heatsink clip load metrology. Package Handling Guidelines Table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate.
Mechanical Specifications 3.7 Processor Materials The Dual-Core Intel® Xeon® Processor 5100 Series is assembled from several components. The basic material properties are described in Table 3-3. Table 3-3. Processor Materials Component 3.8 Material Integrated Heat Spreader (IHS) Nickel over copper Substrate Fiber-reinforced resin Substrate Lands Gold over nickel Processor Land Coordinates Figure 3-5 and Figure 3-6 show the top and bottom view of the processor land coordinates, respectively.
Mechanical Specifications Figure 3-6.
4 Land Listing 4.1 Dual-Core Intel® Xeon® Processor 5100 Series Pin Assignments This section provides sorted land list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number. 4.1.1 Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 1 of 20) Pin Name A03# Pin No. M5 Table 4-1.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 3 of 20) Pin No. Signal Buffer Type Direction Table 4-1. Pin Name Land Listing by Land Name (Sheet 4 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 5 of 20) Pin No. Table 4-1. Land Listing by Land Name (Sheet 6 of 20) Signal Buffer Type Direction Input/Output RESERVED AJ3 Pin Name Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 7 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 8 of 20) Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 9 of 20) Pin No. Signal Buffer Type VCC AG30 Power/Other VCC AG8 VCC AG9 VCC VCC Table 4-1. Land Listing by Land Name (Sheet 10 of 20) Pin No.
Land Listing Table 4-1. Pin Name VCC Land Listing by Land Name (Sheet 11 of 20) Pin No. AN8 Signal Buffer Type Table 4-1. Direction Pin Name Power/Other VCC Land Listing by Land Name (Sheet 12 of 20) Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 13 of 20) Pin Name Pin No. Signal Buffer Type Table 4-1. Direction Pin Name Land Listing by Land Name (Sheet 14 of 20) Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 15 of 20) Pin No. Signal Buffer Type VSS AF29 Power/Other VSS AF3 VSS AF30 VSS VSS Table 4-1. Land Listing by Land Name (Sheet 16 of 20) Pin No.
Land Listing Table 4-1. Land Listing by Land Name (Sheet 17 of 20) Table 4-1. Land Listing by Land Name (Sheet 18 of 20) Pin No.
Land Listing Table 4-1. Pin Name Land Listing by Land Name (Sheet 19 of 20) Pin No. Signal Buffer Type Table 4-1. Direction Land Listing by Land Name (Sheet 20 of 20) Pin Name Pin No.
Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 1 of 20) Pin No. Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 3 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 5 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. AJ8 Land Listing by Land Number (Sheet 7 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 9 of 20) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 11 of 20) Pin Name Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. F11 Land Listing by Land Number (Sheet 13 of 20) Pin Name D23# Table 4-2. Signal Buffer Type Direction Pin No.
Land Listing Table 4-2. Pin No. H3 Land Listing by Land Number (Sheet 15 of 20) Pin Name VSS Signal Buffer Type Direction Power/Other Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 17 of 20) Pin Name Signal Buffer Type M30 VCC Power/Other M4 A07# Source Sync M5 A03# Source Sync Direction Table 4-2. Pin No.
Land Listing Table 4-2. Pin No. Land Listing by Land Number (Sheet 19 of 20) Pin Name Signal Buffer Type Direction U30 VCC Power/Other U4 A13# Source Sync U5 A12# Source Sync U6 A10# Source Sync U7 VSS Power/Other U8 VCC Power/Other V1 MS_ID1 Power/Other Output V2 LL_ID0 Power/Other Output V23 VSS Power/Other V24 VSS V25 VSS V26 V27 Table 4-2. Pin No.
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 7) Name Description Notes I/O A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In subphase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB. A[35:3]# are protected by parity signals AP[1:0]#.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 2 of 7) Type Description Notes BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration (see Section 7.
Signal Definitions Table 5-1. Name D[63:0]# Signal Definitions (Sheet 3 of 7) Type Description Notes I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Signal Definitions Table 5-1. Name DSTBN[3:0]# DSTBP[3:0]# Signal Definitions (Sheet 4 of 7) Type I/O I/O Description Data strobe used to latch in D[63:0]#. Notes 3 Signals Associated Strobes D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3# Data strobe used to latch in D[63:0]#.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 5 of 7) Type Description Notes INIT# I INIT# (Initialization), when asserted, resets integer registers inside all processors without affecting their internal caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 6 of 7) Type Description Notes I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking of these signals.
Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 7) Name Type Description TMS I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all FSB agents. TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.
Signal Definitions 72 Dual-Core Intel® Xeon® Processor 5100 Series Datasheet
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Dual-Core Intel® Xeon® Processor 5100 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications applications. Refer to the Dual-Core Intel® Xeon® Processor 5100 Series Thermal/ Mechanical Design Guidelines for details on system thermal solution design, thermal profiles and environmental considerations. Intel has developed thermal profiles specific to enable the Dual-Core Intel® Xeon® Processor LV 5138, to be used in environments compliant with NEBS* Level 3 ambient operating temperature requirements.
Thermal Specifications The upper point of the thermal profile consists of the Thermal Design Power (TDP) defined in Table 6-8 and the associated TCASE value. It should be noted that the upper point associated with Thermal Profile B (x = TDP and y = TCASE_MAX B @ TDP) represents a thermal solution design point. In actuality the processor case temperature will not reach this value due to TCC activation (see Figure 6-4).
Thermal Specifications Figure 6-1.Dual-Core Intel® Xeon® Processor 5100 Series Thermal Profile 70 TCASE_MAX@TDP Temperature [C] 65 60 Y = 0.385*x +40.0 55 50 45 20 25 30 35 40 45 Power [W] 50 55 60 65 Notes: 1. Please refer to Table 6-2 for discrete points that constitute the thermal profile. 2. Refer to the Dual-Core Intel® Xeon® Processor 5100 Series Thermal/Mechanical Design Guidelines for system and environmental implementation details. Table 6-2.
Thermal Specifications Table 6-3. Dual-Core Intel® Xeon® Processor LV 5138 Thermal Specifications Processor Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 5138 35 5 See Figure 6-2; Table 6-4; Table Notes 1, 2, 3, 4, 5 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications Table 6-4. Dual-Core Intel® Xeon® Processor LV 5138 Nominal Thermal Profile Table Power (W) Table 6-5. Table 6-6. TCASE_MAX (°C) P_PROFILE_MIN_NOMINAL=6.8 50.0 10 52.4 15 56.1 20 59.7 25 63.4 30 67.1 35 70.8 Dual-Core Intel® Xeon® Processor LV 5138 Short Term Thermal Profile Table Power (W) TCASE_MAX (°C) P_PROFILE_MIN_SHORT-TERM=0 60.0 5 63.7 10 67.4 15 71.1 20 74.7 25 78.4 30 82.1 35 85.
Thermal Specifications Figure 6-3. Dual-Core Intel® Xeon® Processor LV 5148 and Dual-Core Intel® Xeon® Processor LV 5128 Thermal Profile 59 TCASE_MAX@TDP Temperature [C] 57 55 53 Y = 0.450*x +40.0 51 49 47 45 20 22 24 26 28 30 Power [W] 32 34 36 38 40 Notes: 1. Please refer to Table 6-7 for discrete points that constitute the thermal profile. 2.
Thermal Specifications 5. 6. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor frequency requirements These values only apply to the B-step of the Dual-Core Intel® Xeon® Processor 5160. For the G-step specifications, please refer to Table 6-1. Figure 6-4.Dual-Core Intel® Xeon® Processor 5160 Thermal Profiles A and B TCASE_MAX_B@TDP is a thermal solution design point. In actuality, units will not significantly exceed TCASE_MAX_A due to TCC activation.
Thermal Specifications Table 6-9. Dual-Core Intel® Xeon® Processor 5160 Thermal Profile A Table (Sheet 2 of 2) Power (W) TCASE_MAX (°C) 70 57.7 75 58.8 80 60.0 Table 6-10. Dual-Core Intel® Xeon® Processor 5160 Thermal Profile B Table Power (W) 6.1.2 TCASE_MAX (°C) P_PROFILE_MIN_B=27 50 35 52.3 40 53.7 45 55.1 50 56.5 55 57.9 60 59.3 65 60.7 70 62.1 75 63.
Thermal Specifications Figure 6-5. Case Temperature (TCASE) Measurement Location Note: Figure is not to scale and is for reference only. 6.2 Processor Thermal Features 6.2.1 Thermal Monitor Features Dual-Core Intel® Xeon® Processor 5100 Series provides two thermal monitor features, Thermal Monitor (TM1) and Enhanced Thermal Monitor (TM2). The Thermal Monitor and Enhanced Thermal Monitor must both be enabled in BIOS for the processor to be operating within specifications.
Thermal Specifications When the Thermal Monitor is enabled, and a high temperature situation exists (that is, TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30 - 50%). Cycle times are processor speed dependent and will decrease as processor core frequencies increase.
Thermal Specifications The second operating point consists of both a lower operating frequency and voltage. The lowest operating frequency is determined by the lowest supported bus ratio (1/6 for the Dual-Core Intel® Xeon® Processor 5100 Series ). When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs rapidly, on the order of 5 µs.
Thermal Specifications If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a ‘1’, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using OnDemand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments.
Thermal Specifications 6.2.5 THERMTRIP# Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 5-1). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 5-1.
Thermal Specifications Figure 6-7. PECI Topology Processor (Socket 0) PECI Pin G5 PECI Host Controller Addr 0x30 Processor (Socket 1) PECI Pin G5 Addr 0x31 For Dual-Core Intel® Xeon® Processor 5100 Series 6.3.1.1 Key Difference with Legacy Diode-Based Thermal Management Fan speed control solutions utilize a TControl value stored in the processor IA32_TEMPERATURE_TARGET MSR. Prior to Dual-Core Intel® Xeon® Processor 5100 Series , TControl represented a diode temperature.
Thermal Specifications Figure 6-8. Temperature Data Format Comparison: Thermal Diode vs. PECI Digital Thermal Sensor TCC Activation Temperature TControl Setting Max Fan Speed (RPM) PECI = 0C Tdiode = 80C PECI = -10C Min Tdiode = 70C PECI = -20C Temperature Conceptual Fan Control Diagram on Desktop Platforms (not intended to depict actual implementation) 6.3.1.
Thermal Specifications Table 6-11. Supported PECI Command Functions and Codes Command Function 6.3.2.3 Code Comments Ping() n/a This command targets a valid PECI device address followed by zero Write Length and zero Read Length.
Thermal Specifications 90 Dual-Core Intel® Xeon® Processor 5100 Series Datasheet
Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Dual-Core Intel® Xeon® Processor 5100 Series samples its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these options, please refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. 7.2.2.1 HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction.
Features Table 7-2. Extended HALT Maximum Power B-step Max Unit Notes PEXTENDED_HALT Dual-Core Intel® Xeon® Processor LV 5148 Symbol Extended HALT State Power Parameter Min Typ 14 W 1 PEXTENDED_HALT Dual-Core Intel® Xeon® Processor 5100 Series Extended HALT State Power 24/27 W 1,2 PEXTENDED_HALT Dual-Core Intel® Xeon® Processor 5160 Extended HALT State Power 24 W 1 Note: 1. The specification is at Tcase = 50oC and nominal Vcc.
Features Figure 7-1.
Features While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. The PBE# signal can be driven when the processor is in Stop-Grant state.
Features Enhanced Intel SpeedStep® Technology creates processor performance states (Pstates) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep® Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage.
Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Dual-Core Intel® Xeon® Processor 5100 Series will be offered as an Intel boxed processor.
Boxed Processor Specifications Figure 8-2. Boxed Dual-Core Intel® Xeon® Processor 5100 Series 2U Passive Heat Sink Figure 8-3. 2U Passive Dual-Core Intel® Xeon® Processor 5100 Series Thermal Solution (Exploded View) Notes: 1. The heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. 2. The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components in an exploded view. 3.
Boxed Processor Specifications 8.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor. 8.2.1 Boxed Processor Heat Sink Dimensions (CEK) The boxed processor will be shipped with an unattached thermal solution. Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8-4 through Figure 8-8.
Boxed Processor Specifications Figure 8-4.
Boxed Processor Specifications Figure 8-5.
Boxed Processor Specifications Figure 8-6.
Boxed Processor Specifications Figure 8-7.
Boxed Processor Specifications Figure 8-8.
Boxed Processor Specifications Figure 8-9.
Boxed Processor Specifications Figure 8-10.
Boxed Processor Specifications 8.2.2 Boxed Processor Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor, a dual processor system will have up to 2100 grams total mass in the heat sinks. This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration.
Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. Table 8-1. Table 8-2.
Boxed Processor Specifications 8.3.2.1 1U Passive/3U+ Active Combination Heat Sink Solution (1U Rack Passive) In the 1U configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 15 cfm at 0.38 in. H2O (25.5 m3/hr at 94.6 Pa) of flow impedance. The duct should be carefully designed to minimize the airflow bypass around the heatsink. It is assumed that a 40°C TLA is met.
Boxed Processor Specifications The other items listed in Figure 8-3 that are required to compete this solution will be shipped with either the chassis or boards.
Debug Tools Specifications 9 Debug Tools Specifications Please refer to the Debug Port Design Guide for UP/DP Systems and the appropriate platform design guidelines for information regarding debug tool specifications. Section 1.3 provides collateral details. 9.1 Debug Port System Requirements The Dual-Core Intel® Xeon® Processor 5100 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug.
Debug Tools Specifications 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.
