FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM71-00101-5E FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL
FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL FUJITSU LIMITED
PREFACE ■ Objectives and intended reader The FR* family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32-bit RISC based computing. The architecture is optimized for use in microcontroller CPU cores for built-in control applications where high-speed control is required. This manual is written for engineers involved in the development of products using the FR family of microcontrollers.
■ Organization of this manual This manual consists of the following 7 chapters and 1 appendix: CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations. CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU. CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU.
• • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information.
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CONTENTS CHAPTER 1 1.1 1.2 1.3 FR FAMILY OVERVIEW .............................................................................. 1 Features of the FR Family CPU Core ................................................................................................. 2 Sample Configuration of an FR Family Device ................................................................................... 3 Sample Configuration of the FR Family CPU ........................................................................
CHAPTER 5 5.1 5.2 5.3 5.4 5.4.1 5.4.2 Pipeline Operation ............................................................................................................................ Pipeline Operation and Interrupt Processing .................................................................................... Register Hazards .............................................................................................................................. Delayed Branching Processing ...........................
7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 7.43 7.44 7.45 7.46 7.47 7.48 7.49 7.50 7.51 7.52 7.53 7.54 7.55 7.56 7.57 7.58 7.59 7.60 7.61 7.62 7.63 7.64 7.65 7.66 7.67 7.68 7.69 7.70 7.71 7.72 7.73 7.74 7.75 7.76 7.77 7.78 7.79 7.80 7.81 MULU (Multiply Unsigned Word Data) ............................................................................................ MULH (Multiply Half-word Data) .....................................................................................................
7.82 7.83 7.84 7.85 7.86 7.87 7.88 7.89 7.90 7.91 7.92 7.93 7.94 7.95 7.96 7.97 7.98 7.99 7.100 7.101 7.102 7.103 7.104 7.105 7.106 7.107 7.108 7.109 7.110 7.111 7.112 7.113 7.114 7.115 7.116 7.117 7.118 7.119 7.120 7.121 7.122 MOV (Move Word Data in Source Register to Destination Register) ............................................. MOV (Move Word Data in Source Register to Destination Register) .............................................
7.123 7.124 7.125 7.126 7.127 7.128 7.129 7.130 7.131 7.132 7.133 7.134 7.135 STILM (Set Immediate Data to Interrupt Level Mask Register) ...................................................... ADDSP (Add Stack Pointer and Immediate Data) .......................................................................... EXTSB (Sign Extend from Byte Data to Word Data) ...................................................................... EXTUB (Unsign Extend from Byte Data to Word Data) .............................
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Main changes in this edition Page - Changes (For details, refer to main body.) Be sure to refer to the "Check Sheet" for the latest cautions on development. is changed. ("Check Sheet" is seen at the following support page... is deleted.) "■ Objectives and intended reader" is changed. ( "FR" → "FR*" ) "■ Objectives and intended reader" is changed. ( " *: " is added. ) i "PREFACE" is changed. ( "■ Trademark" is added. ) "PREFACE" is changed.
Page Changes (For details, refer to main body.) "4.3.1 User Interrupts" is changed. ( "External" → "User" ), ( "external" → "user" ) "■ Overview of User Interrupts" is changed. ( "External" → "User" ) "■ Overview of User Interrupts" is changed. ( "Interrupts are referred to as "external" when they originate outside the CPU." is deleted. ) 38 "■ Conditions for Acceptance of User Interrupt Requests" is changed. ( "External" → "User" ) "■ Conditions for Acceptance of User Interrupt Requests" is changed.
Page Changes (For details, refer to main body.) 87 "7.15 AND (And Word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0100 0010 0011" is added.) 89 "7.16 ANDH (And Half-word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0101 0010 0011" is added. ) 91 "7.17 ANDB (And Byte Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0110 0010 0011" is added. ) 92 "7.
Page Changes (For details, refer to main body.) 136 "7.42 DIV3 (Correction when Remainder is 0)" is changed. ( "Instruction bit pattern : 1001 1111 0110 0000" is added. ) 137 "7.43 DIV4S (Correction Answer for Signed Division)" is changed. ( "Instruction bit pattern : 1001 1111 0111 0000" is added. ) 138 "7.44 LSL (Logical Shift to the Left Direction)" is changed. ( "Instruction bit pattern : 1011 0110 0010 0011" is added. ) 141 "7.47 LSR (Logical Shift to the Right Direction)" is changed.
Page Changes (For details, refer to main body.) 163 "7.67 LDUB (Load Byte Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0010 0010 0011" is added. ) 165 "7.69 ST (Store Word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0100 0010 0011" is added. ) 166 "7.70 ST (Store Word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0000 0010 0011" is added. ) 168 "7.72 ST (Store Word Data in Register to Memory)" is changed.
Page Changes (For details, refer to main body.) "7.88 CALL (Call Subroutine)" is changed. ( "extension for use as the branch destination address" → "extension" ) 185 "7.88 CALL (Call Subroutine)" is changed. ( "CALL 120H" → " CALL label ... label: ; CALL instruction address + 122H" ) "7.88 CALL (Call Subroutine)" is changed. ( "Instruction bit pattern : 1101 0000 1001 0000" is added. ) 186 "7.89 CALL (Call Subroutine)" is changed. ( "Instruction bit pattern : 1001 0111 0001 0001" is added. ) 187 "7.
Page 198 Changes (For details, refer to main body.) "7.96 CALL:D (Call Subroutine)" is changed. ( "CALL : D 120H LDI : 8 #0, R2 ; Instruction placed in delay slot" → "CALL:D label LDI : 8 #0, R2 ; Instruction placed in delay slot ... label: ; CALL: D instruction address + 122H" ) "7.96 CALL:D (Call Subroutine)" is changed. ( "Instruction bit pattern : 1101 1000 1001 0000" is added. ) 200 "7.97 CALL:D (Call Subroutine)" is changed. ( "Instruction bit pattern : 1001 1111 0001 0001" is added. ) 202 "7.
Page Changes (For details, refer to main body.) 238 "7.121 ANDCCR (And Condition Code Register and Immediate Data)" is changed. ( "Instruction bit pattern : 1000 0011 1111 1110" is added. ) 239 "7.122 ORCCR (Or Condition Code Register and Immediate Data)" is changed. ( "Instruction bit pattern : 1001 0011 0001 0000" is added. ) 240 "7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)" is changed. ( "Instruction bit pattern : 1000 0111 0001 0100" is added. ) 242 "7.
Page Changes (For details, refer to main body.) "A.1 Symbols Used in Instruction Lists" is chenged. ● Symbols in Mnemonic and Operation Columns is changed. i8 .............( "128 to 255" → "0 to 255" ) "A.1 Symbols Used in Instruction Lists" is chenged. ● Symbols in Mnemonic and Operation Columns is changed. ( "Note: Data from -128 to -1 is handled as data from 128 to 255." is deleted. ) "A.1 Symbols Used in Instruction Lists" is chenged. ● Symbols in Mnemonic and Operation Columns is changed. i20 ........
Page 267 Changes (For details, refer to main body.) "Table A.2-6 Shift Instructions (9 Instructions)" is changed. ( "Ri <<(u4+16) → Ri" → "Ri <<{u4+16} → Ri" ) ( "Ri >>(u4+16) → Ri" → "Ri >>{u4+16} → Ri" ) ( "Ri >>(u4+16) → Ri" → "Ri >>{u4+16} → Ri" ) 272 "Table A.2-13 Direct Addressing Instructions (14 Instructions)" is changed. ("disp8" → "dir8"), ("disp9" → "dir9"), ("disp10" → "dir10") 273 "Table A.2-16 Other Instructions (16 Instructions)" is changed. ("i8" → "u8") 276 "Table B.
CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations. 1.1 Features of the FR Family CPU Core 1.2 Sample Configuration of an FR Family Device 1.
CHAPTER 1 FR FAMILY OVERVIEW 1.1 Features of the FR Family CPU Core The FR family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32-bit "RISC" based computing. The architecture is optimized for use in microcontroller CPU cores for built-in control applications where high-speed control is required.
CHAPTER 1 FR FAMILY OVERVIEW 1.2 Sample Configuration of an FR Family Device FR family devices have block configuration with bus connections between individual modules. This enables module connections to be altered as necessary to accommodate a wide variety of functional configurations. Figure 1.2-1 shows an example of the configuration of an FR family device. ■ Sample Configuration of an FR Family Device Figure 1.
CHAPTER 1 FR FAMILY OVERVIEW 1.3 Sample Configuration of the FR Family CPU The FR family CPU core features a block configuration organized around generalpurpose registers, with dedicated registers, "ALU" units, multipliers and other features included for each specific application. Figure 1.3-1 shows a sample configuration of an FR family CPU. ■ Sample Configuration of the FR Family CPU Instruction data Instruction decoder Figure 1.
CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU. Memory architecture includes the allocation of memory space as well as methods used to access memory. 2.1 FR Family Memory Space 2.2 Bit Order and Byte Order 2.
CHAPTER 2 MEMORY ARCHITECTURE 2.1 FR Family Memory Space The FR family controls memory space in byte units, and provides linear designation of 32-bit spaces. Also, to enhance instruction efficiency, specific areas of memory are allocated for use as direct address areas and vector table areas. ■ Memory Space Figure 2.1-1 illustrates memory space in the FR family. For a detailed description of the direct address area, see Section "2.1.1 Direct Address Area", and for the vector table area, see Section "2.1.
CHAPTER 2 MEMORY ARCHITECTURE 2.1.1 Direct Address Area The lower portion of the address space is used for the direct address area. Instructions that specify direct addresses allow you to access this area without the use of generalpurpose registers, using only the operand information in the instruction itself. The size of the address area that can be specified by direct addressing varies according to the length of the data being transferred.
CHAPTER 2 MEMORY ARCHITECTURE 2.1.2 Vector Table Area An area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to store "EIT" vector addresses. ■ Overview of Vector Table Areas An area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to store "EIT" vector addresses. Data written to this area includes entry addresses for exception processing, interrupt processing and trap processing.
CHAPTER 2 MEMORY ARCHITECTURE ■ Contents of Vector Table Areas A vector table is composed of entry addresses for each of the "EIT" processing programs. Each table contains some values whose use is fixed according to the CPU architecture, and some that vary according to the types of built-in peripheral circuits present. Table 2.1-1 shows the structure of a vector table area. Table 2.
CHAPTER 2 MEMORY ARCHITECTURE 2.2 Bit Order and Byte Order This section describes the order in which three types of data, 8, 16, and 32 bits, are placed in the memory in the FR family. In the FR family, the bit number increases approaching the MSB, and the byte number increases approaching the lowest address value. ■ Bit Order and Byte Order Bit order in the general-purpose register is that the larger numbers are placed in the vicinity of the MSB while the smaller numbers are near the LSB.
CHAPTER 2 MEMORY ARCHITECTURE 2.3 Word Alignment In the FR family, the type of data length used determines restrictions on the designation of memory addresses (word alignment). ■ Program Restrictions on Word Alignment When using half-word instruction length, memory addresses must be accessed in multiples of two. With branching instructions and other instructions that may result in attempting to store odd numbered values to the "PC", the lowest value in the "PC" will be read as "0".
CHAPTER 2 MEMORY ARCHITECTURE 12
CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU. 3.1 FR Family Register Configuration 3.2 General-purpose Registers 3.
CHAPTER 3 REGISTER DESCRIPTIONS 3.1 FR Family Register Configuration FR family devices use two types of registers, general-purpose registers and dedicated registers. • General-purpose registers: Store computation data and address information • Dedicated registers: Store information for specific applications Figure 3.1-1 shows the configuration of registers in FR family devices. ■ FR Family Register Configuration Figure 3.
CHAPTER 3 REGISTER DESCRIPTIONS 3.2 General-purpose Registers The FR family CPU uses general-purpose registers to hold the results of various calculations, as well as information about addresses to be used as pointers for memory access. These registers also have special functions with certain types of instructions. ■ Overview of General-purpose Registers The FR family CPU has sixteen (16) general-purpose registers each 32 bits in length.
CHAPTER 3 REGISTER DESCRIPTIONS ● R14 (Frame Pointer: FP) • Index register for load/store to memory instructions [Example: LD @(R14, disp10), Ri] • Frame pointer for reserve/release of dynamic memory area [Example: ENTER #u10] ● R15 (Stack Pointer: SP) • Index register for load/store to memory instructions [Example: LD @(R15, udisp6), Ri] • Stack pointer [Example: LD @R15+, Ri] • Stack pointer for reserve/release of dynamic memory area [Example: ENTER #u10] ■ Relation between "R15" and Stack Pointer The
CHAPTER 3 REGISTER DESCRIPTIONS 3.3 Dedicated Registers The FR family has six 32-bit registers reserved for various special purposes, plus one 64-bit dedicated register for multiplication and division operations. ■ Dedicated Registers The following seven dedicated registers are provided. For details, see the descriptions in Sections "3.3.1 Program Counter (PC)" through "3.3.6 Multiplication/Division Register (MD)".
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.1 Program Counter (PC) This register indicates the address containing the instruction that is currently executing. Following a reset, the contents of the PC are set to the reset entry address contained in the vector table. ■ Overview of the Program Counter This register indicates the address containing the instruction that is currently executing.
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.2 Program Status (PS) The program status (PS) indicates the status of program execution, and consists of the following three parts: • Interrupt level mask register (ILM) • System condition code register (SCR) • Condition code register (CCR) ■ Overview of Program Status Register The program status register consists of sections that set the interrupt enable level, control the program trace break function in the CPU, and indicate the status of instruction execution.
CHAPTER 3 REGISTER DESCRIPTIONS Figure 3.3-4 "ILM" Register Functions FR family CPU ILM Interrupt request 1 29 ICR Peripheral I flag 25 Comp 29>25 AND Interrupt controller Interrupt activated Activation OK ● Range of ILM Program Setting Values If the original value of the register is in the range 16 to 31, the new value may be set in the range 16 to 31. If an instruction attempts to set a value between 0 and 15, that value will be converted to "setting value + 16" and then transferred.
CHAPTER 3 REGISTER DESCRIPTIONS ■ Condition Code Register (CCR: Bit 07 to bit 00) ● Bit Configuration of the "CCR" Figure 3.3-6 Bit Configuration of the "CCR" CCR 07 06 05 04 03 02 01 00 - - S I N Z V C Initial value: --00XXXXB ● "CCR" Functions • "S" Flag This flag selects the stack pointer to be used. The value "0" selects the system stack pointer (SSP), and "1" selects the user stack pointer (USP). RETI instruction is executable only when the S flag is "0".
CHAPTER 3 REGISTER DESCRIPTIONS ■ Note on PS Register Because of prior processing of the PS register by some commands, a break may be brought in an interrupt processing subroutine during the use of a debugger or flag display content in the PS register may be changed with the following exceptional operations. In both cases, right re-processing is designed to execute after returning from the EIT. So, operations before and after EIT are performed conforming to the specifications.
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.3 Table Base Register (TBR) The Table Base Register (TBR) designates the table containing the entry address for "EIT" operations. ■ Overview of the Table Base Register The Table Base Register (TBR) designates the table containing the entry address for "EIT" operations. When an "EIT" condition occurs, the address of the vector reference is determined by the sum of the contents of this register and the vector offset corresponding to the "EIT" operation. Figure 3.
CHAPTER 3 REGISTER DESCRIPTIONS ■ Table Base Register Configuration Figure 3.3-8 shows the bit configuration of the table base register. Figure 3.3-8 Table Base Register Bit Configuration Bit no. 31 00 TBR ■ Table Base Register Functions ● Vector Table Reference Addresses Addresses for vector reference are generated by adding the contents of the "TBR" register and the vector offset value, which is determined by the type of interrupt used.
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.4 Return Pointer (RP) The return pointer (RP) is a register used to contain the program counter (PC) value during execution of call instructions, in order to assure return to the correct address after the call instruction has executed. ■ Overview of the Return Pointer The contents of the return pointer (RP) depend on the type of instruction.
CHAPTER 3 REGISTER DESCRIPTIONS ■ Return Pointer Configuration Figure 3.3-11 shows the bit configuration of the return pointer. Figure 3.3-11 Return Pointer Bit Configuration Bit no. 31 00 RP ■ Return Pointer Functions ● Return Pointer in Multiple "CALL" Instructions Because the "RP" does not have a stack configuration, it is necessary to first execute a save when calling one subroutine from another subroutine. ● Initial Value of Return Pointer The initial value is undefined.
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP) The system stack pointer (SSP) and user stack pointer (USP) are registers that refer to the stack area. The "S" flag in the "CCR" determines whether the "SSP" or "USP" is used. Also, when an "EIT" event occurs, the program counter (PC) and program status (PS) values are saved to the stack area designated by the "SSP", regardless of the value of the "S" flag at that time.
CHAPTER 3 REGISTER DESCRIPTIONS Figure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13, @-R15" when "S" Flag = 1 Before execution of ST R13,@-R15 After execution of ST R13,@-R15 Memory space 00000000H SSP 12345678H USP 76543210H R13 17263540H ???????? ???????? SSP 12345678H USP 7654320CH R13 17263540H FFFFFFFFH S CCR Memory space 00000000H S CCR 1 17263540H FFFFFFFFH 1 ■ Stack Pointer Configuration Figure 3.
CHAPTER 3 REGISTER DESCRIPTIONS 3.3.6 Multiplication/Division Register (MD) The multiplication/division register (MD) is a 64-bit register used to contain the result of multiplication operations, as well as the dividend and result of division operations. ■ Overview of the Multiplication/Division Register The multiplication/division register (MD) is a register used to contain the result of multiplication operations, as well as the dividend and result of division operations.
CHAPTER 3 REGISTER DESCRIPTIONS ■ Configuration of the "MD" Register Figure 3.3-17 shows the bit configuration of the "MD". Figure 3.3-17 Bit Configuration of the "MD" Bit no. 31 00 MDH MDL ■ Functions of the "MD" ● Storing Results of Multiplication and Division The results of multiplication operations are stored in the "MDH" (higher 32 bits) and "MDL" (lower 32 bits) registers.
CHAPTER 4 RESET AND "EIT" PROCESSING This chapter describes reset and "EIT" processing in the FR family CPU. A reset is a means of forcibly terminating the currently executing process, initializing the entire device, and restarting the program from the beginning. "EIT" processing, in contrast, terminates the currently executing process and saves restart information to the memory, then transfers control to a predetermined processing program.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.1 Reset Processing 4.2 Basic Operations in "EIT" Processing 4.3 Interrupts 4.4 Exception Processing 4.5 Traps 4.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.1 Reset Processing A reset is a means of forcibly terminating the currently executing process, initializing the entire device, and restarting the program from the beginning. Resets are used to start the LSI operating from its initial state, as well as to recover from error conditions. ■ Reset Operations When a reset is applied, the CPU terminates processing of the instruction executing at that time and goes into inactive status until the reset is canceled.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.2 Basic Operations in "EIT" Processing Interrupts, exceptions and traps are similar operations applied under partially differing conditions. Each "EIT" event involves terminating the execution of instructions, saving information for restarting, and branching to a designated processing program. ■ Basic Operations in "EIT" Processing The FR family device processes "EIT" events as follows.
CHAPTER 4 RESET AND "EIT" PROCESSING ■ Vector Table Configuration Vector tables are located in the main memory, occupying an area of 1 Kbyte beginning with the address shown in the TBR. These areas are intended for use as a table of entry addresses for "EIT" processing, however in applications where vector tables are not required, this area can be used as a normal instruction or data area. Figure 4.2-2 shows the structure of the vector table. (Example of 32-source) Figure 4.
CHAPTER 4 RESET AND "EIT" PROCESSING ■ Saved Registers Except in the case of reset processing, the values of the "PS" and "PC" are saved to the stack as designated by the "SSP", regardless of the value of the "S" flag in the "CCR". No save operation is used in reset processing. Figure 4.2-3 illustrates the saving of the values of the "PC" and "PS" in "EIT" processing. Figure 4.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.3 Interrupts Interrupts originate independently of the instruction sequence. They are processed by saving the necessary information to resume the currently executing instruction sequence, and then starting the processing routine corresponding to the type of interrupt that has occurred. There are two types of interrupt sources.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.3.1 User Interrupts User interrupts originate as requests from peripheral circuits. Each interrupt request is assigned an interrupt level, and it is possible to mask requests according to their level values. This section describes conditions for acceptance of user interrupts, as well as their operation and uses. ■ Overview of User Interrupts User interrupts originate as requests from peripheral circuits.
CHAPTER 4 RESET AND "EIT" PROCESSING ■ Time to Start of Interrupt Processing The time required to start interrupt processing can be expressed as a maximum of "n + 6" cycles from the start of the instruction currently executing when the interrupt was received, where "n" represents the number of execution cycles in the instruction. If the instruction includes memory access, or insufficient instructions are present, the corresponding number of wait cycles must be added.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.3.2 Non-maskable Interrupts (NMI) Non-maskable interrupts (NMI) are interrupts that cannot be masked. "NMI" requests can be produced when "NMI" external signal pin input to the microcontroller is active. This section describes conditions for the acceptance of "NMI" interrupts, as well as their operation and uses. ■ Overview of Non-maskable Interrupts Non-maskable interrupts (NMI) are interrupts that cannot be masked.
CHAPTER 4 RESET AND "EIT" PROCESSING ■ "PC" Values Saved for Non-maskable Interrupts When an "NMI" is accepted by the processor, those instructions in the pipeline that cannot be interrupted in time will be executed. The remainder of the instructions will be canceled, and will not be processed after the interrupt. The "EIT" processing sequence saves "PC" values to the system stack representing the addresses of canceled instructions.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4 Exception Processing Exceptions originate from within the instruction sequence. Exceptions are processed by first saving the necessary information to resume the currently executing instruction, and then starting the processing routine corresponding to the type of exception that has occurred. ■ Overview of Exception Processing Exceptions originate from within the instruction sequence.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4.1 Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined. This section describes the operation, time requirements and uses of undefinedinstruction exceptions. ■ Overview of Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5 Traps Traps originate from within the instruction sequence. Traps are processed by first saving the necessary information to resume processing from the next instruction in the sequence, and then starting the processing routine corresponding to the type of trap that has occurred.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.1 "INT" Instructions The "INT" instruction is used to create a software trap. This section describes the operation, time requirements, program counter (PC) values saved, and other information of the "INT" instruction. ■ Overview of the "INT" Instruction The "INT #u8" instruction is used to create a software trap with the interrupt number designated in the operand.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.2 "INTE" Instruction The "INTE" instruction is used to create a software trap for debugging. This section describes the operation, time requirements, program counter (PC) values saved, and other information of the "INTE" instruction. ■ Overview of the "INTE" Instruction The "INTE" instruction is used to create a software trap for debugging. This instruction allows the use of emulators.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.3 Step Trace Traps Step trace traps are traps used by debuggers. This type of trap can be created for each individual instruction in a sequence by setting the "T" flag in the system condition code register (SCR) in the program status (PS). This section describes conditions for the generation, operations, program counter (PC) values saved, and other information of step trace traps. ■ Overview of Step Trace Traps Step trace traps are traps used by debuggers.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.4 Coprocessor Not Found Traps Coprocessor not found traps are generated by executing coprocessor instructions using coprocessors not found in the system. This section describes conditions for the generation of coprocessor not found traps, in addition to operation, program counter (PC) values saved, and other information.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5.5 Coprocessor Error Trap A coprocessor error trap is generated when an error has occurred in a coprocessor operation and the CPU executes another coprocessor instruction involving the same coprocessor. This section describes conditions for the generation, operations, and program counter (PC) values saved of coprocessor error traps.
CHAPTER 4 RESET AND "EIT" PROCESSING ■ Saving and Restoring Coprocessor Error Information When a coprocessor is used in a multi-tasking environment, the internal resources of the coprocessor become part of the system context. Thus whenever context switching occurs, it is necessary to save or restore the contents of the coprocessor. Problems arise when there are hidden coprocessor errors remaining from former tasks at the time of context switching.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.6 Priority Levels When multiple "EIT" requests occur at the same time, priority levels are used to select one source and execute the corresponding "EIT" sequence. After the "EIT" sequence is completed, "EIT" request detection is applied again to enable processing of multiple "EIT" requests. Acceptance of certain types of "EIT" requests can mask other factors.
CHAPTER 4 RESET AND "EIT" PROCESSING ■ Priority of Multiple Processes When the acceptance of an "EIT" source results in the masking of other sources, the priority of execution of simultaneously occurring "EIT" handlers is as shown in Table 4.6-2. Table 4.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU This chapter presents precautionary information related to the use of the FR family CPU. 5.1 Pipeline Operation 5.2 Pipeline Operation and Interrupt Processing 5.3 Register Hazards 5.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.1 Pipeline Operation The FR family CPU processes all instructions using a 5-stage pipeline operation. This makes it possible to process nearly all instructions within one cycle. ■ Overview of Pipeline Operation In a pipeline operation the steps by which the CPU interprets and executes instructions are divided into several cycles, so that instructions can be processed simultaneously in successive cycles.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.2 Pipeline Operation and Interrupt Processing The FR family CPU processes all instructions through pipeline operation. Therefore, particularly for instructions that start hardware events, it is possible for contradictory conditions to exist before and after an instruction.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.3 Register Hazards The FR family CPU executes program steps in the order in which they are written, and is therefore equipped with a function that detects the occurrence of register hazards and stops pipeline processing when necessary.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ■ Interlocking Instructions which are relatively slow in loading data to the CPU may cause register hazards that cannot be handled by register bypassing. In the example in Figure 5.3-3, data required for the "ID" stage of the "SUB" instruction must be loaded to the CPU in the "MA" stage of the "LD" instruction, creating a hazard that cannot be avoided by the bypass function. Figure 5.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.4 Delayed Branching Processing Because the FR family CPU features pipeline operation, branching instructions must first be loaded before they are executed. Delayed branching processing is the function to execute the loaded instruction, and allows to accelerate processing speeds.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU • AND ANDH ANDB OR ORH ORB EOR EORH EORB Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri Rj, @Ri • BANDH BANDL BORH BORL BEORH BEORL BTSTH BTSTL #u4, @Ri #u4, @Ri #u4, @Ri #u4, @Ri #u4, @Ri #u4, @Ri #u4, @Ri #u4, @Ri • MUL MULU MULH MULUH Rj, Ri Rj, Ri Rj, Ri Rj, Ri • LD @R15+, PS • LDM0 LDM1 STM0 STM1 ENTER XCHB (reglist) (reglist) (reglist) (reglist) #u10 @Rj, Ri • DMOV DMOV DMOV DMOV DMOVH DMOVH DMOVB DMOVB @dir10, @R13
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.4.1 Processing Non-delayed Branching Instructions The FR family CPU processes non-delayed branching instructions in the order in which the program is written, introducing a 1-cycle delay in execution speed if branching takes place. ■ Examples of Processing Non-delayed Branching Instructions Figure 5.4-1 shows an example of processing a non-delayed branching instruction when branching conditions are satisfied.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5.4.2 Processing Delayed Branching Instructions The FR family CPU processes delayed branching instructions with an apparent execution speed of 1 cycle, regardless of whether branching conditions are satisfied or not satisfied. When branching occurs, this is one cycle faster than using non-delayed branching instructions. However, the apparent order of instruction processing is inverted in cases where branching occurs.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ■ Examples of Programing Delayed Branching Instructions An example of programing a delayed branching instruction is shown below. . . LD @R10, R1 LD @R11, R2 ADD R1, R3 BNE:D TestOK ST R2, @R12 ADD #4, R12 ; not satisfy . . . TestOK: ST . .
CHAPTER 6 INSTRUCTION OVERVIEW This chapter presents an overview of the instructions used with the FR family CPU. All FR family CPU instructions are in 16-bit fixed length format, except for immediate data transfer instructions which may exceed 16 bits in length. This format enables the creation of a compact object code and smoother pipeline processing. 6.1 Instruction Formats 6.
CHAPTER 6 INSTRUCTION OVERVIEW 6.1 Instruction Formats The FR family CPU uses six types of instruction format, TYPE-A through TYPE-F. ■ Instruction Formats All instructions used by the FR family CPU are written in the six formats shown in Figure 6.1-1. Figure 6.
CHAPTER 6 INSTRUCTION OVERVIEW ■ Relation between Bit Pattern "Rs" and Register Values Table 6.1-2 shows the relation between dedicated register numbers and field bit pattern values. Table 6.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 Instruction Notation Formats FR family CPU instructions are written in the following three notation formats. • Calculations are designated by a mnemonic placed between operand 1 and operand 2, with the results stored at operand 2. • Operations are designated by a mnemonic, and use operand 1. • Operations are designated by a mnemonic. ■ Instruction Notation Formats FR family CPU instructions are written in the following 3 notation formats.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS This chapter presents each of the execution instructions used by the FR family assembler, in reference format. The execution instructions used by the FR family CPU are classified as follows.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 68 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) 7.5 ADDN (Add Word Data of Source Register to Destination Register) 7.6 ADDN (Add Immediate Data to Destination Register) 7.7 ADDN2 (Add Immediate Data to Destination Register) 7.8 SUB (Subtract Word Data in Source Register from Destination Register) 7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.40 DIV1 (Main Process of Division) 7.41 DIV2 (Correction when Remainder is 0) 7.42 DIV3 (Correction when Remainder is 0) 7.43 DIV4S (Correction Answer for Signed Division) 7.44 LSL (Logical Shift to the Left Direction) 7.45 LSL (Logical Shift to the Left Direction) 7.46 LSL2 (Logical Shift to the Left Direction) 7.47 LSR (Logical Shift to the Right Direction) 7.48 LSR (Logical Shift to the Right Direction) 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.77 STH (Store Half-word Data in Register to Memory) 7.78 STH (Store Half-word Data in Register to Memory) 7.79 STB (Store Byte Data in Register to Memory) 7.80 STB (Store Byte Data in Register to Memory) 7.81 STB (Store Byte Data in Register to Memory) 7.82 MOV (Move Word Data in Source Register to Destination Register) 7.83 MOV (Move Word Data in Source Register to Destination Register) 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 DMOVB (Move Byte Data from Direct Address to Register) 7.111 DMOVB (Move Byte Data from Register to Direct Address) 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) 7.114 LDRES (Load Word Data in Memory to Resource) 7.115 STRES (Store Word Data in Resource to Memory) 7.116 COPOP (Coprocessor Operation) 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.1 ADD (Add Word Data of Source Register to Destination Register) Adds word data in "Rj" to word data in "Ri", stores results to "Ri". ■ ADD (Add Word Data of Source Register to Destination Register) Assembler format: ADD Rj, Ri Operation: Ri + Rj → Ri Flag change: Execution cycles: N Z V C C C C C N : Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z : Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.2 ADD (Add 4-bit Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with zero extension to the word data in "Ri", stores results to the "Ri". ■ ADD (Add 4-bit Immediate Data to Destination Register) Assembler format: ADD #i4, Ri Operation: Ri + extu(i4) → Ri Flag change: Execution cycles: N Z V C C C C C N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.3 ADD2 (Add 4-bit Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to the word data in "Ri", stores results to "Ri". The way a "C" flag of this instruction varies is the same as the ADD instruction ; it is different from that of the SUB instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) Adds the word data in "Rj" to the word data in "Ri" and carry bit, stores results to "Ri". ■ ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) Assembler format: ADDC Rj, Ri Operation: Ri + Rj + C → Ri Flag change: Execution cycles: N Z V C C C C C N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.5 ADDN (Add Word Data of Source Register to Destination Register) Adds the word data in "Rj" and the word data in "Ri", stores results to "Ri" without changing flag settings.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.6 ADDN (Add Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with zero extension to the word data in "Ri", stores the results to "Ri" without changing flag settings.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.7 ADDN2 (Add Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to word data in "Ri", stores the results to "Ri" without changing flag settings.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.8 SUB (Subtract Word Data in Source Register from Destination Register) Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri". ■ SUB (Subtract Word Data in Source Register from Destination Register) Assembler format: SUB Rj, Ri Operation: Ri – Rj → Ri Flag change: Execution cycles: N Z V C C C C C N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) Subtracts the word data in "Rj" and the carry bit from the word data in "Ri", stores results to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.10 SUBN (Subtract Word Data in Source Register from Destination Register) Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri" without changing the flag settings.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.11 CMP (Compare Word Data in Source Register and Destination Register) Subtracts the word data in "Rj" from the word data in "Ri", places results in the condition code register (CCR). ■ CMP (Compare Word Data in Source Register and Destination Register) Assembler format: CMP Rj, Ri Operation: Ri – Rj Flag change: Execution cycles: N Z V C C C C C N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.12 CMP (Compare Immediate Data of Source Register and Destination Register) Subtracts the result of the higher 28 bits of 4-bit immediate data with zero extension from the word data in "Ri", places results in the condition code register (CCR).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.13 CMP2 (Compare Immediate Data and Destination Register) Subtracts the result of the higher 28 bits of 4-bit immediate(from -16 to -1) data with minus extension from the word data in "Ri", places results in the condition code register (CCR).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.14 AND (And Word Data of Source Register to Destination Register) Takes the logical AND of the word data in "Rj" and the word data in "Ri", stores the results to "Ri". ■ AND (And Word Data of Source Register to Destination Register) Assembler format: AND Rj, Ri Operation: Ri and Rj → Ri Flag change: N Z V C C C – – N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.15 AND (And Word Data of Source Register to Data in Memory) Takes the logical AND of the word data at memory address "Ri" and the word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: AND R2, @R3 Instruction bit pattern : 1000 0100 0010 0011 R2 1 1 1 1 0 0 0 0 R2 1 1 1 1 0 0 0 0 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 1 0 1 0 1 0 Memory 12345678 1234567C 1234567C N Z V C CCR 1 0 1 0 0 0 0 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 87
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.16 ANDH (And Half-word Data of Source Register to Data in Memory) Takes the logical AND of the half-word data at memory address "Ri" and the half-word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ANDH R2, @R3 Instruction bit pattern : 1000 0101 0010 0011 R2 0 0 0 0 1 1 0 0 R2 0 0 0 0 1 1 0 0 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 1 0 Memory 12345678 1234567A 1234567A N Z V C CCR 1 0 0 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 89
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.17 ANDB (And Byte Data of Source Register to Data in Memory) Takes the logical AND of the byte data at memory address "Ri" and the byte data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ANDB R2, @R3 Instruction bit pattern : 1000 0110 0010 0011 R2 0 0 0 0 0 0 1 0 R2 0 0 0 0 0 0 1 0 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 1 12345679 Memory 12345678 12345679 N Z V C CCR 1 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 91
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.18 OR (Or Word Data of Source Register to Destination Register) Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the results to "Ri". ■ OR (Or Word Data of Source Register to Destination Register) Assembler format: OR Rj, Ri Operation: Ri or Rj → Ri Flag change: N Z V C C C – – N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.19 OR (Or Word Data of Source Register to Data in Memory) Takes the logical OR of the word data at memory address "Ri" and the word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: OR R2, @R3 Instruction bit pattern : 1001 0100 0010 0011 R2 1 1 1 1 0 0 0 0 R2 1 1 1 1 0 0 0 0 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 1 0 1 0 1 0 Memory 12345678 1234567C 1234567C N Z V C CCR 0 0 0 0 Before execution 94 1 1 1 1 1 0 1 0 N Z V C CCR 0 0 0 0 After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.20 ORH (Or Half-word Data of Source Register to Data in Memory) Takes the logical OR of the half-word data at memory address "Ri" and the half-word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ORH R2, @R3 Instruction bit pattern : 1001 0101 0010 0011 R2 0 0 0 0 1 1 0 0 R2 0 0 0 0 1 1 0 0 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 1 0 Memory 12345678 1234567A 1234567A N Z V C CCR 0 0 0 0 Before execution 96 1 1 1 0 N Z V C CCR 0 0 0 0 After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.21 ORB (Or Byte Data of Source Register to Data in Memory) Takes the logical OR of the byte data at memory address "Ri" and the byte data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ORB R2, @R3 Instruction bit pattern : 1001 0110 0010 0011 R2 0 0 0 0 0 0 1 1 R2 0 0 0 0 0 0 1 1 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 12345679 Memory 12345678 12345679 N Z V C CCR 0 0 0 0 Before execution 98 1 1 N Z V C CCR 0 0 0 0 After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register) Takes the logical exclusive OR of the word data in "Ri" and the word data in "Rj", stores the results to "Ri". ■ EOR (Exclusive Or Word Data of Source Register to Destination Register) Assembler format: EOR Rj, Ri Operation: Ri eor Rj → (Ri) Flag change: N Z V C C C – – N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory) Takes the logical exclusive OR of the word data at memory address "Ri" and the word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EOR R2, @R3 Instruction bit pattern : 1001 1100 0010 0011 R2 1 1 1 1 0 0 0 0 R2 1 1 1 1 0 0 0 0 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 1 0 1 0 1 0 1234567C Memory 12345678 1234567C N Z V C CCR 0 1 0 1 1 0 1 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 101
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) Takes the logical exclusive OR of the half-word data at memory address "Ri" and the half-word data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EORH R2, @R3 Instruction bit pattern : 1001 1101 0010 0011 R2 0 0 0 0 1 1 0 0 R2 0 0 0 0 1 1 0 0 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 1 0 1234567A Memory 12345678 1234567A N Z V C CCR 0 1 1 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 103
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) Takes the logical exclusive OR of the byte data at memory address "Ri" and the byte data in "Rj", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: EORB R2, @R3 Instruction bit pattern : 1001 1110 0010 0011 R2 0 0 0 0 0 0 1 1 R2 0 0 0 0 0 0 1 1 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 0 Memory 12345678 12345679 12345679 N Z V C CCR 0 1 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 105
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BANDL #0, @R3 Instruction bit pattern : 1000 0000 0000 0011 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 1 12345679 Memory 12345678 12345679 N Z V C CCR 1 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 107
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BANDH #0, @R3 Instruction bit pattern : 1000 0001 0000 0011 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 1 1 12345679 Memory 12345678 12345679 N Z V C CCR 0 1 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 109
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Takes the logical OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BORL #1, @R3 Instruction bit pattern : 1001 0000 0001 0011 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 0 0 12345679 Memory 12345678 12345679 N Z V C CCR 0 1 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 111
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Takes the logical OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BORH #1, @R3 Instruction bit pattern : 1001 0001 0001 0011 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 0 0 12345679 Memory 12345678 12345679 N Z V C CCR 1 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 113
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) Takes the logical exclusive OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BEORL #1, @R3 Instruction bit pattern : 1001 1000 0001 0011 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 0 0 12345679 Memory 12345678 12345679 N Z V C CCR 0 1 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 115
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) Takes the logical exclusive OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", stores the results to the memory address corresponding to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this request.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: BEORH #1, @R3 Instruction bit pattern : 1001 1001 0001 0011 R3 1 2 3 4 5 6 7 8 R3 1 2 3 4 5 6 7 8 Memory 12345678 0 0 12345679 Memory 12345678 12345679 N Z V C CCR 1 0 0 0 0 0 Before execution N Z V C CCR 0 0 0 0 After execution 117
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory address "Ri", places the results in the condition code register (CCR).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory address "Ri", places the results in the condition code register (CCR).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.34 MUL (Multiply Word Data) Multiplies the word data in "Rj" by the word data in "Ri" as signed numbers, and stores the resulting signed 64-bit data with the high word in the multiplication/division register (MDH), and the low word in the multiplication/division register (MDL).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MUL R2, R3 Instruction bit pattern : 1010 1111 0010 0011 R2 0 0 0 0 0 0 0 2 R2 0 0 0 0 0 0 0 2 R3 8 0 0 0 0 0 0 1 R3 8 0 0 0 0 0 0 1 MDH x x x x x x x x MDH F F F F F F F F MDL x x x x x x x x MDL 0 0 0 0 0 0 0 2 N Z V C CCR 0 0 0 0 Before execution N Z V C CCR 0 0 1 0 After execution 121
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.35 MULU (Multiply Unsigned Word Data) Multiplies the word data in "Rj" by the word data in "Ri" as unsigned numbers, and stores the resulting unsigned 64-bit data with the high word in the multiplication/ division register (MDH), and the low word in the multiplication/division register (MDL).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULU R2, R3 Instruction bit pattern : 1010 1011 0010 0011 R2 0 0 0 0 0 0 0 2 R2 0 0 0 0 0 0 0 2 R3 8 0 0 0 0 0 0 1 R3 8 0 0 0 0 0 0 1 MDH x x x x x x x x MDH 0 0 0 0 0 0 0 1 MDL x x x x x x x x MDL 0 0 0 0 0 0 0 2 N Z V C N Z V C CCR 0 0 0 0 Before execution CCR 0 0 1 0 After execution 123
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.36 MULH (Multiply Half-word Data) Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the lower 16 bits of "Ri" as signed numbers, and stores the resulting signed 32-bit data in the multiplication/division register (MDL). The multiplication/division register (MDH) is undefined.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULH R2, R3 Instruction bit pattern : 1011 1111 0010 0011 R2 F E D C B A 9 8 R2 F E D C B A 9 8 R3 0 1 2 3 4 5 6 7 R3 0 1 2 3 4 5 6 7 MDH x x x x x x x x MDH x x x x MDL x x x x x x x x MDL E D 2 F 0 B 2 8 N Z V C N Z V C CCR 0 0 0 0 Before execution x x x x CCR 1 0 0 0 After execution 125
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.37 MULUH (Multiply Unsigned Half-word Data) Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the lower 16 bits of "Ri" as unsigned numbers, and stores the resulting unsigned 32-bit data in the multiplication/division register (MDL). The multiplication/division register (MDH) is undefined.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MULUH R2, R3 Instruction bit pattern : 1011 1011 0010 0011 R2 F E D C B A 9 8 R2 F E D C B A 9 8 R3 0 1 2 3 4 5 6 7 R3 0 1 2 3 4 5 6 7 MDH x x x x x x x x MDH x x x x MDL x x x x x x x x MDL 3 2 9 6 0 B 2 8 N Z V C CCR 0 0 0 0 Before execution x x x x N Z V C CCR 0 0 0 0 After execution 127
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.38 DIV0S (Initial Setting Up for Signed Division) This command is used for signed division in which the multiplication/division register (MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the "MDL" and the remainder in the multiplication/division register (MDH). The value of the sign bit in the "MDL" and "Ri" is used to set the "D0" and "D1" flag bits in the system condition code register (SCR).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV0S R2 Instruction bit pattern : 1001 0111 0100 0010 R2 0 F F F F F F F R2 0 F F F F F F F MDH 0 0 0 0 0 0 0 0 MDH F F F F F F F F MDL F F F F F F F 0 MDL F F F F F F F 0 D1 D0 T D1 D0 T SCR x x 0 SCR Before execution After execution Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), signed calculation R2 R2 R2 ... DIV0S DIV1 DIV1 ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.39 DIV0U (Initial Setting Up for Unsigned Division) This command is used for unsigned division in which the multiplication/division register (MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the "MDL" register and the remainder in the multiplication/division register (MDH). The "MDH" and bits "D1" and "D0" are cleared to "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV0U R2 Instruction bit pattern : 1001 0111 0101 0010 R2 0 0 F F F F F F R2 0 0 F F F F F F MDH 0 0 0 0 0 0 0 0 MDH 0 0 0 0 0 0 0 0 MDL 0 F F F F F F 0 MDL 0 F F F F F F 0 D1 D0 T D1 D0 T SCR x x 0 SCR Before execution After execution Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), unsigned calculation ... DIV0U R2 DIV1 R2 DIV1 R2 ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.40 DIV1 (Main Process of Division) This instruction is used in unsigned division. It should be used in combinations such as DIV0U and DIV1 x 32.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV1 R2 Instruction bit pattern : 1001 0111 0110 0010 R2 0 0 F F F F F F R2 0 0 F F F F F F MDH 0 0 F F F F F F MDH 0 1 0 0 0 0 0 0 MDL 0 0 0 0 0 0 0 0 MDL 0 0 0 0 0 0 0 1 D1 D0 T D1 D0 T SCR 0 0 0 SCR N Z V C CCR 0 0 0 0 Before execution 0 0 0 N Z V C CCR 0 0 0 0 After execution 133
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.41 DIV2 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combinations such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DIV2 R2 Instruction bit pattern : 1001 0111 0111 0010 R2 0 0 F F F F F F R2 0 0 F F F F F F MDH 0 0 F F F F F F MDH 0 0 0 0 0 0 0 0 MDL 0 0 0 0 0 0 0 F MDL 0 0 0 0 0 0 0 F D1 D0 T SCR 0 0 0 D1 D0 T SCR N Z V C CCR 0 0 0 0 Before execution 0 0 0 N Z V C CCR 0 1 0 0 After execution 135
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.42 DIV3 (Correction when Remainder is 0) This instruction is used in signed division. It should be used in combinations such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.43 DIV4S (Correction Answer for Signed Division) This instruction is used in signed division. It should be used in combinations such as DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.44 LSL (Logical Shift to the Left Direction) Makes a logical left shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.45 LSL (Logical Shift to the Left Direction) Makes a logical left shift of the word data in "Ri" by "u4" bits, stores the result to "Ri". ■ LSL (Logical Shift to the Left Direction) Assembler format: LSL #u4, Ri Operation: Ri << u4 → Ri Flag change: N Z V C C C – C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.46 LSL2 (Logical Shift to the Left Direction) Makes a logical left shift of the word data in "Ri" by "{u4 + 16}" bits, stores the results to "Ri". ■ LSL2 (Logical Shift to the Left Direction) Assembler format: LSL2 #u4, Ri Operation: Ri << {u4 + 16} → Ri Flag change: N Z V C C C – C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.47 LSR (Logical Shift to the Right Direction) Makes a logical right shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.48 LSR (Logical Shift to the Right Direction) Makes a logical right shift of the word data in "Ri" by "u4" bits, stores the result to "Ri". ■ LSR (Logical Shift to the Right Direction) Assembler format: LSR #u4, Ri Operation: Ri >> u4 → Ri Flag change: N Z V C C C – C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.49 LSR2 (Logical Shift to the Right Direction) Makes a logical right shift of the word data in "Ri" by "{u4 + 16}" bits, stores the result to "Ri". ■ LSR2 (Logical Shift to the Right Direction) Assembler format: LSR2 #u4, Ri Operation: Ri >> {u4 + 16} → Ri Flag change: N Z V C 0 C – C N: Cleared Z: Set when the operation result is "0", cleared otherwise. V: Unchanged C: Holds the bit value shifted last.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.50 ASR (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri". Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the shift range is 0 to 31 bits.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.51 ASR (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "u4" bits, stores the result to "Ri". ■ ASR (Arithmetic Shift to the Right Direction) Assembler format: ASR #u4, Ri Operation: Ri >> u4 → Ri Flag change: N Z V C C C – C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.52 ASR2 (Arithmetic Shift to the Right Direction) Makes an arithmetic right shift of the word data in "Ri" by "{u4 + 16}" bits, stores the result to "Ri". ■ ASR2 (Arithmetic Shift to the Right Direction) Assembler format: ASR2 #u4, Ri Operation: Ri >> {u4 + 16} → Ri Flag change: N Z V C C C – C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register) Loads 1 word of immediate data to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register) Extends the 20-bit immediate data with 12 zeros in the higher bits, loads to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register) Extends the 8-bit immediate data with 24 zeros in the higher bits, loads to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.56 LD (Load Word Data in Memory to Register) Loads the word data at memory address "Rj" to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.57 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R13 + Rj)" to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.58 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R14 + o8 × 4)" to "Ri". The value "o8" is a signed calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.59 LD (Load Word Data in Memory to Register) Loads the word data at memory address "(R15 + u4 × 4)" to "Ri". The value "u4" is an unsigned calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.60 LD (Load Word Data in Memory to Register) Loads the word data at memory address "R15" to "Rj", and adds 4 to the value of "R15". If "R15" is given as parameter "Ri", the value read from the memory will be loaded into memory address "R15".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.61 LD (Load Word Data in Memory to Register) Loads the word data at memory address "R15" to dedicated register "Rs", and adds 4 to the value of "R15". If the number of a non-existent register is given as parameter "Rs", the read value "Ri" will be ignored.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LD @ R15 +, MDH Instruction bit pattern : 0000 0111 1000 0100 R15 1 2 3 4 5 6 7 4 R15 1 2 3 4 5 6 7 8 MDH x x x x MDH 8 7 6 5 4 3 2 1 x x x x 12345670 Memory 12345670 Memory 12345674 8 7 6 5 4 3 2 1 12345674 8 7 6 5 4 3 2 1 Before execution 156 After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.62 LD (Load Word Data in Memory to Program Status Register) Loads the word data at memory address "R15" to the program status (PS), and adds 4 to the value of "R15". At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM" settings between 16 and 31 can be entered.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LD @ R15 +, PS Instruction bit pattern : 0000 0111 1001 0000 R15 1 2 3 4 5 6 7 4 R15 1 2 3 4 5 6 7 8 PS F F F F F 8 D 5 PS F F F 8 F 8 C 0 12345670 Memory 12345670 Memory 12345674 F F F 8 F 8 C 0 12345674 F F F 8 F 8 C 0 Before execution 158 After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.63 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "Rj", loads to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.64 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "(R13 + Rj)", loads to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.65 LDUH (Load Half-word Data in Memory to Register) Extends with zeros the half-word data at memory address "(R14 + o8 × 2)", loads to "Ri". The value "o8" is a signed calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.66 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "Rj", loads to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.67 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "(R13 + Rj)", loads to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.68 LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address "(R14 + o8)", loads to "Ri". The value "o8" is a signed calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.69 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "Rj".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.70 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R13 + Rj)".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.71 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R14 + o8 × 4)". The value "o8" is a signed calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.72 ST (Store Word Data in Register to Memory) Loads the word data in "Ri" to memory address "(R15 + u4 × 4)". The value "u4" is an unsigned calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.73 ST (Store Word Data in Register to Memory) Subtracts 4 from the value of "R15", stores the word data in "Ri" to the memory address indicated by the new value of "R15". If "R15" is given as the parameter "Ri", the data transfer will use the value of "R15" before subtraction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.74 ST (Store Word Data in Register to Memory) Subtracts 4 from the value of "R15", stores the word data in dedicated register "Rs" to the memory address indicated by the new value of "R15". If a non-existent dedicated register is given as "Rs", undefined data will be transferred.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.75 ST (Store Word Data in Program Status Register to Memory) Subtracts 4 from the value of "R15", stores the word data in the program status (PS) to the memory address indicated by the new value of "R15".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.76 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "Rj".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.77 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "(R13 + Rj)".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.78 STH (Store Half-word Data in Register to Memory) Stores the half-word data in "Ri" to memory address "(R14 + o8 × 2)". The value "o8" is a signed calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.79 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "Rj".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.80 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "(R13 + Rj)".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.81 STB (Store Byte Data in Register to Memory) Stores the byte data in "Ri" to memory address "(R14 + o8)". The value "o8" is a signed calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.82 MOV (Move Word Data in Source Register to Destination Register) Moves the word data in "Rj" to "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.83 MOV (Move Word Data in Source Register to Destination Register) Moves the word data in dedicated register "Rs" to general-purpose register "Ri". If the number of a non-existent dedicated register is given as "Rs", undefined data will be transferred.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.84 MOV (Move Word Data in Program Status Register to Destination Register) Moves the word data in the program status (PS) to general-purpose register "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.85 MOV (Move Word Data in Source Register to Destination Register) Moves the word data in general-purpose register "Ri" to dedicated register "Rs". If the number of a non-existent register is given as parameter "Rs", the read value "Ri" will be ignored.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.86 MOV (Move Word Data in Source Register to Program Status Register) Moves the word data in general-purpose register Ri to the program status (PS). At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM" settings between 16 and 31 can be entered. If data in the range 0 to 15 is loaded from "Ri", the value 16 will be added to that data before being transferred to the "ILM".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: MOV R3, PS Instruction bit pattern : 0000 0111 0001 0011 R3 F F F 3 F 8 D 5 R3 F F F 3 F 8 D 5 PS x x x x PS F F F 3 F 8 D 5 x x x x Before execution After execution 183
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.87 JMP (Jump) This is a branching instruction with no delay slot. Branches to the address indicated by "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.88 CALL (Call Subroutine) This is a branching instruction with no delay slot. After storing the address of the next instruction in the return pointer (RP), branch to the address indicated by "lavel12" relative to the value of the program counter (PC). When calculating the address, double the value of "rel11" as a signed extension.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.89 CALL (Call Subroutine) This is a branching instruction with no delay slot. After storing the address of the next instruction in the return pointer (RP), a branch to the address indicated by "Ri" occurs.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.90 RET (Return from Subroutine) This is a branching instruction with no delay slot. Branches to the address indicated by the return pointer (RP).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.91 INT (Software Interrupt) Stores the values of the program counter (PC) and program status (PS) to the stack indicated by the system stack pointer (SSP) for interrupt processing. Writes "0" to the "S" flag in the condition code register (CCR), and uses the "SSP" as the stack pointer for the following steps. Writes "0" to the "I" flag (interrupt enable flag) in the "CCR" to disable external interrupts.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: INT #20H Instruction bit pattern : 0001 1111 0010 0000 R15 4 0 0 0 0 0 0 0 R15 7 F F F F F F 8 SSP 8 0 0 0 0 0 0 0 SSP 7 F F F F F F 8 TBR 0 0 0 F F C 0 0 TBR 0 0 0 F F C 0 0 USP 4 0 0 0 0 0 0 0 USP 4 0 0 0 0 0 0 0 PC 8 0 8 8 8 0 8 6 PC 6 8 0 9 6 8 0 0 PS F F F F F 8 F 0 PS F F F F F 8 C 0 S I N Z V C CCR 1 1 0 0 0 0 S I N Z V C CCR Memory 0 0 0 0 0 0 Memory 000FFF7C 6 8 0 9 6 8 0 0 000FFF7C 6 8 0 9 6 8 0 0 7FFFFFF8 x x
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.92 INTE (Software Interrupt for Emulator) This software interrupt instruction is used for debugging. It stores the values of the program counter (PC) and program status (PS) to the stack indicated by the system stack pointer (SSP) for interrupt processing. It writes "0" to the "S" flag in the condition code register (CCR), and uses the "SSP" as the stack pointer for the following steps.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: INTE Instruction bit pattern : 1001 1111 0011 0000 R15 4 0 0 0 0 0 0 0 R15 7 F F F F F F 8 SSP 8 0 0 0 0 0 0 0 SSP 7 F F F F F F 8 USP 4 0 0 0 0 0 0 0 USP 4 0 0 0 0 0 0 0 TBR 0 0 0 F F C 0 0 TBR 0 0 0 F F C 0 0 PC 8 0 8 8 8 0 8 6 PC 6 8 0 9 6 8 0 0 PS F F F 5 F 8 F 0 PS F F E 4 F 8 D 0 ILM 1 0 1 0 1 ILM S I N Z V C CCR 1 1 0 0 0 0 0 0 1 0 0 S I N Z V C CCR Memory 0 1 0 0 0 0 Memory 000FFFD8 6 8 0 9 6 8 0 0 000FFFD8 6
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.93 RETI (Return from Interrupt) Loads data from the stack indicated by "R15" to the program counter (PC) and program status (PS), and retakes control from the interrupt handler. This instruction requires the S flag in the register (CCR) to be executed in a state of "0". Do not manipulate the S flag in the normal interrupt handler; use it in a state of 0 as it is. This instruction has no delay slot.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: RETI Instruction bit pattern : 1001 0111 0011 0000 R15 7 F F F F F F 8 R15 4 0 0 0 0 0 0 0 SSP 7 F F F F F F 8 SSP 8 0 0 0 0 0 0 0 USP 4 0 0 0 0 0 0 0 USP 4 0 0 0 0 0 0 0 PC F F 0 0 9 0 B C PC 8 0 8 8 8 0 8 8 PS F F F 0 F 8 D 4 PS F F F 3 F 8 F 1 ILM 1 0 0 0 0 ILM S I N Z V C CCR 0 1 0 1 0 0 1 0 0 1 1 S I N Z V C CCR Memory 1 1 0 0 0 1 Memory 7FFFFFF8 8 0 8 8 8 0 8 8 7FFFFFF8 8 0 8 8 8 0 8 8 7FFFFFFC F F F 3 F 8 F 1 7F
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.94 Bcc (Branch Relative if Condition Satisfied) This branching instruction has no delay slot. If the conditions established for each particular instruction are satisfied, branch to the address indicated by "label9" relative to the value of the program counter (PC). When calculating the address, double the value of "rel8" as a signed extension. If conditions are not satisfied, no branching can occur. Conditions for each instruction are listed in Table 7.94-1.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Execution cycles: Branch: Not branch: 2 cycles 1 cycle Instruction format: MSB 1 Example: LSB 1 1 0 cc rel8 BHI label ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.95 JMP:D (Jump) This branching instruction has a delay slot. Branches to the address indicated by "Ri". ■ JMP:D (Jump) Assembler format: JMP : D @Ri Operation: Ri → PC Flag change: N Z V C – – – – N, Z, V, and C: Unchanged Execution cycles: 1 cycle Instruction format: MSB 1 0 0 1 1 JMP : D @R1 LDI : 8 #0FFH, R1 1 1 1 0 0 0 0 Ri ; Instruction placed in delay slot ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.96 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the "RP", branch to the address indicated by "label12" relative to the value of the program counter (PC). When calculating the address, double the value of "rel11" as a signed extension.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: CALL:D label LDI : 8 #0, R2 ; Instruction placed in delay slot ... label: ; CALL: D instruction address + 122H Instruction bit pattern : 1101 1000 1001 0000 R2 x x x x PC RP x x x x R2 0 0 0 0 0 0 0 0 F F 8 0 0 0 0 0 PC F F 8 0 0 1 2 2 x x x x RP F F 8 0 0 0 0 4 x x x x Before execution of "CALL" instruction After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.97 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the "RP", it branches to the address indicated by "Ri".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS CALL : D @R1 LDI : 8 #1, R1 ; Instruction placed in delay slot ... Example: Instruction bit pattern : 1001 1111 0001 0001 R1 F F F F F 8 0 0 R1 0 0 0 0 0 0 0 1 PC 8 0 0 0 F F F E PC F F F F F 8 0 0 RP x x x x RP 8 0 0 1 0 0 0 2 x x x x Before execution of "CALL" instruction After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.98 RET:D (Return from Subroutine) This is a branching instruction with a delay slot. Branches to the address indicated by the "RP".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS RET : D MOV R0, R1 ; Instruction placed in delay slot ... Example: Instruction bit pattern : 1001 1111 0010 0000 R0 0 0 1 1 2 2 3 3 R0 0 0 1 1 2 2 3 3 R1 x x x x x x x x R1 0 0 1 1 2 2 3 3 PC F F F 0 8 8 2 0 PC 8 0 0 0 A E 8 6 RP 8 0 0 0 A E 8 6 RP 8 0 0 0 A E 8 6 Before execution of "RET" instruction After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.99 Bcc:D (Branch Relative if Condition Satisfied) This is a branching instruction with a delay slot. If the conditions established for each particular instruction are satisfied, branch to the address indicated by "label9" relative to the value of the program counter (PC). When calculating the address, double the value of "rel8" as a signed extension. If conditions are not satisfied, no branching can occur. Conditions for each instruction are listed in Table 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Execution cycles: 1 cycle Instruction format: MSB 1 BHI:D label LDI :8 1 1 1 #255, R1 cc rel8 ; Instruction placed in delay slot ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.100 DMOV (Move Word Data from Direct Address to Register) Transfers, to "R13", the word data at the direct address corresponding to 4 times the value of "dir8".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.101 DMOV (Move Word Data from Register to Direct Address) Transfers the word data in "R13" to the direct address corresponding to 4 times the value of "dir8".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) Transfers the word data at the direct address corresponding to 4 times the value of "dir8" to the address indicated in "R13". After the data transfer, it increments the value of "R13" by 4.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @88H, @R13+ Instruction bit pattern : 0000 1100 0010 0010 R13 F F F F 1 2 4 8 R13 Memory 00000088 1 4 1 4 2 1 3 5 Memory 00000088 1 4 1 4 2 1 3 5 FFFF1248 x x x x x x x x FFFF1248 1 4 1 4 2 1 3 5 FFFF124C x x x x x x x x FFFF124C x x x x Before execution 208 F F F F 1 2 4 C x x x x After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfers the word data at the address indicated in "R13" to the direct address corresponding to 4 times the value "dir8". After the data transfer, it increments the value of "R13" by 4.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @R13+, @54H Instruction bit pattern : 0001 1100 0001 0101 R13 F F F F 1 2 4 8 R13 Memory Memory 00000054 x x x x x x x x 00000054 8 9 4 7 9 1 A F FFFF1248 8 9 4 7 9 1 A F FFFF1248 8 9 4 7 9 1 A F FFFF124C x x x x x x x x FFFF124C x x x x x x x x Before execution 210 F F F F 1 2 4 C After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address) Decrements the value of "R15" by 4, then transfers word data at the direct address corresponding to 4 times the value of "dir8" to the address indicated in "R15".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @2CH, @ – R15 Instruction bit pattern : 0000 1011 0000 1011 R15 7 F F F F F 8 8 R15 Memory 0000002C 8 2 A 2 8 2 A 9 Memory 0000002C 8 2 A 2 8 2 A 9 7FFFFF84 x x x x x x x x 7FFFFF84 8 2 A 2 8 2 A 9 7FFFFF88 x x x x x x x x 7FFFFF88 x x x x Before execution 212 7 F F F F F 8 4 x x x x After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfers the word data at the address indicated in "R15" to the direct address corresponding to 4 times the value "dir8". After the data transfer, it increments the value of "R15" by 4.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOV @R15+, @38H Instruction bit pattern : 0001 1011 0000 1110 R15 7 F F E E E 8 0 R15 Memory Memory 00000038 x x x x x x x x 00000038 8 3 4 3 8 3 4 A 7FFEEE80 8 3 4 3 8 3 4 A 7FFEEE80 8 3 4 3 8 3 4 A 7FFEEE84 x x x x x x x x 7FFEEE84 x x x x x x x x Before execution 214 7 F F E E E 8 4 After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.106 DMOVH (Move Half-word Data from Direct Address to Register) Transfers the half-word data at the direct address corresponding to 2 times the value "dir8" to "R13". Uses zeros to extend the higher 16 bits of data.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.107 DMOVH (Move Half-word Data from Register to Direct Address) Transfers the half-word data from "R13" to the direct address corresponding to 2 times the value "dir8".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address) Transfers the half-word data at the direct address corresponding to 2 times the value "dir8" to the address indicated by "R13". After the data transfer, it increments the value of "R13" by 2.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVH @88H, @R13+ Instruction bit pattern : 0000 1101 0100 0100 R13 F F 0 0 0 0 5 2 R13 F F 0 0 0 0 5 4 Memory 00000088 1 3 7 4 00000088 1 3 7 4 FF000052 x x x x FF000052 1 3 7 4 FF000054 x x x x FF000054 x x x x Before execution 218 Memory After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address) Transfers the half-word data at the address indicated by "R13" to the direct address corresponding to 2 times the value "dir8". After the data transfer, it increments the value of "R13" by 2.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVH @R13+, @52H Instruction bit pattern : 0001 1101 0010 1001 R13 F F 8 0 1 2 2 0 R13 F F 8 0 1 2 2 2 Memory 00000052 00000052 8 9 3 3 FF801220 8 9 3 3 FF801220 8 9 3 3 FF801222 x x x x FF801222 x x x x Before execution 220 Memory x x x x After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 DMOVB (Move Byte Data from Direct Address to Register) Transfers the byte data at the address indicated by the value "dir8" to "R13". Uses zeros to extend the higher 24 bits of data.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.111 DMOVB (Move Byte Data from Register to Direct Address) Transfers the byte data from "R13" to the direct address indicated by the value "dir8".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) Moves the byte data at the direct address indicated by the value "dir8" to the address indicated by "R13". After the data transfer, it increments the value of "R13" by 1.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVB @71H, @R13+ Instruction bit pattern : 0000 1110 0111 0001 R13 8 8 0 0 1 2 3 4 R13 8 8 0 0 1 2 3 5 Memory 00000071 9 9 00000071 9 9 88001234 x x 88001234 9 9 88001235 x x 88001235 x x Before execution 224 Memory After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) Transfers the byte data at the address indicated by "R13" to the direct address indicated by the value "dir8". After the data transfer, it increments the value of "R13" by 1.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: DMOVB @R13+, @57H Instruction bit pattern : 0001 1110 0101 0111 R13 F F 8 0 1 2 2 0 R13 F F 8 0 1 2 2 1 Memory 00000057 x x 00000057 5 5 FF801220 5 5 FF801220 5 5 FF801221 x x FF801221 x x Before execution 226 Memory After execution
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.114 LDRES (Load Word Data in Memory to Resource) Transfers the word data at the address indicated by "Ri" to the resource on channel "u4". Increments the value of "Ri" by 4.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.115 STRES (Store Word Data in Resource to Memory) Transfers the word data at the resource on channel "u4" to the address indicated by "Ri". Increments the value of "Ri" by 4.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.116 COPOP (Coprocessor Operation) Transfers the 16-bit data consisting of parameters "CC", "CRj", "CRi" to the coprocessor indicated by channel number "u4". Basically, this operation is a calculation between registers within the coprocessor. The calculation process indicated by the value "CC" is carried out between coprocessor registers "CRj" and "CRi".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPOP #15, #1, CR3, CR4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. MSB 0 LSB 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.116-1 will have the following effect on coprocessor operation. Table 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register) Transfers the 16-bit data consisting of parameters "CC", "Rj", "CRi" to the coprocessor indicated by channel number "u4", then on the next cycle transfers the contents of CPU general-purpose register "Rj" to that coprocessor. Basically, this operation transfers data to a register within the coprocessor.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPLD #15, #4, R8, CR1 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the contents of general-purpose register "R8" are transferred through the bus to that coprocessor. MSB 0 LSB 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.118 COPST (Store 32-bit Data from Coprocessor Register to Register) Transfers the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor indicated by channel number "u4", then on the next cycle loads the data output by the coprocessor into CPU general-purpose register "Ri". Basically, this operation transfers data from a register within the coprocessor.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPST #15, #4, CR2, R4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the output data of the coprocessor are transferred through the bus to that coprocessor. MSB 0 LSB 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 Assuming that the coprocessor indicated by channel 15 is a single-precision floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register) Transfers the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor indicated by channel number u4, then on the next cycle loads the data output by the coprocessor to CPU general-purpose register "Ri". Basically, this operation transfers data from a register within the coprocessor.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: COPSV #15, #4, CR2, R4 16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next, the data output by the coprocessor is loaded into the CPU through the data bus. Note that no "coprocessor error" trap will be generated even if the coprocessor designated by the value "u4" has generated an error in a previous operation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.120 NOP (No Operation) This instruction performs no operation. ■ NOP (No Operation) Assembler format: NOP Operation: This instruction performs no operation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.121 ANDCCR (And Condition Code Register and Immediate Data) Takes the logical AND of the byte data in the condition code register (CCR) and the immediate data, and returns the results into the "CCR". ■ ANDCCR (And Condition Code Register and Immediate Data) Assembler format: ANDCCR #u8 Operation: CCR and u8 → CCR Flag change: S I N Z V C C C C C C C S, I, N, Z, V, and C: Varies according to results of calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.122 ORCCR (Or Condition Code Register and Immediate Data) Takes the logical OR of the byte data in the condition code register (CCR) and the immediate data, and returns the results into the "CCR". ■ ORCCR (Or Condition Code Register and Immediate Data) Assembler format: ORCCR #u8 Operation: CCR or u8 → CCR Flag change: S I N Z V C C C C C C C S, I, N, Z, V, and C: Varies according to results of calculation.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) Transfers the immediate data to the interrupt level mask register (ILM) in the program status (PS). Only the lower 5 bits (bit4 to bit0) of the immediate data are valid. At the time this instruction is executed, if the value of the interrupt level mask register (ILM) is in the range 16 to 31, only new "ILM" settings between 16 and 31 can be entered.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.124 ADDSP (Add Stack Pointer and Immediate Data) Adds 4 times the immediate data as a signed extended value, to the value in "R15".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.125 EXTSB (Sign Extend from Byte Data to Word Data) Extends the byte data indicated by "Ri" to word data as a signed binary value.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.126 EXTUB (Unsign Extend from Byte Data to Word Data) Extends the byte data indicated by "Ri" to word data as an unsigned binary value.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.127 EXTSH (Sign Extend from Byte Data to Word Data) Extends the half-word data indicated by "Ri" to word data as a signed binary value.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.128 EXTUH (Unsigned Extend from Byte Data to Word Data) Extends the half-word data indicated by "Ri" to word data as an unsigned binary value.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.129 LDM0 (Load Multiple Registers) The "LDM0" instruction accepts registers in the range R0 to R7 as members of the parameter "reglist". (See Table 7.129-1.) Registers are processed in ascending numerical order. ■ LDM0 (Load Multiple Registers) Assembler format: LDM0 (reglist) Operation: The following operations are repeated according to the number of registers specified in the parameter "reglist".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LDM0 (R3, R4) Instruction bit pattern : 1000 1100 0001 1000 R3 x x x x x x x x R3 9 0 B C 9 3 6 3 R4 x x x x x x x x R4 8 3 4 3 8 3 4 A R15 7 F F F F F C 0 R15 7 F F F F F C 8 Memory Memory 7FFFFFC0 9 0 B C 9 3 6 3 7FFFFFC0 9 0 B C 9 3 6 3 7FFFFFC4 8 3 4 3 8 3 4 A 7FFFFFC4 8 3 4 3 8 3 4 A 7FFFFFC8 x x x x 7FFFFFC8 x x x x x x x x Before execution x x x x After execution 247
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.130 LDM1 (Load Multiple Registers) The LDM1 instruction accepts registers in the range R8 to R15 as members of the parameter "reglist" (See Table 7.130-1.). Registers are processed in ascending numerical order. If "R15" is specified in the parameter "reglist", the final contents of "R15" will be read from memory.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Table 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.131 STM0 (Store Multiple Registers) The "STM0" instruction accepts registers in the range R0 to R7 as members of the parameter "reglist" (See Table 7.131-1.) . Registers are processed in descending numerical order. ■ STM0 (Store Multiple Registers) Assembler format: STM0 (reglist) Operation: The following operations are repeated according to the number of registers specified in the parameter "reglist".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: STM0 (R2, R3) Instruction bit pattern : 1000 1110 0011 0000 R2 9 0 B C 9 3 6 3 R2 9 0 B C 9 3 6 3 R3 8 3 4 3 8 3 4 A R3 8 3 4 3 8 3 4 A R15 7 F F F F F C 8 R15 7 F F F F F C 0 Memory Memory 7FFFFFC0 x x x x x x x x 7FFFFFC0 9 0 B C 9 3 6 3 7FFFFFC4 x x x x x x x x 7FFFFFC4 8 3 4 3 8 3 4 A 7FFFFFC8 x x x x x x x x 7FFFFFC8 x x x x x x x x Before execution After execution 251
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.132 STM1 (Store Multiple Registers) The "STM1" instruction accepts registers in the range R8 to R15 as members of the parameter "reglist" (See Table 7.132-1.). Registers are processed in descending numerical order. If "R15" is specified in the parameter "reglist", the contents of "R15" retained before the instruction is executed will be written to memory.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: STM1 (R10, R11, R12) Instruction bit pattern : 1000 1111 0011 1000 R10 8 F E 3 9 E 8 A R10 8 F E 3 9 E 8 A R11 9 0 B C 9 3 6 3 R11 9 0 B C 9 3 6 3 R12 8 D F 7 8 8 E 4 R12 8 D F 7 8 8 E 4 R15 7 F F F F F C C R15 7 F F F F F C 0 Memory Memory 7FFFFFC0 x x x x x x x x 7FFFFFC0 8 F E 3 9 E 8 A 7FFFFFC4 x x x x x x x x 7FFFFFC4 9 0 B C 9 3 6 3 7FFFFFC8 x x x x x x x x 7FFFFFC8 8 D F 7 8 8 E 4 7FFFFFCC x x x x x x x x 7FFFFFCC
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.133 ENTER (Enter Function) This instruction is used for stack frame generation processing for high level languages. The value "u8" is calculated as an unsigned value.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: ENTER #0CH Instruction bit pattern : 0000 1111 0000 0011 R14 8 0 0 0 0 0 0 0 R14 7 F F F F F F 4 R15 7 F F F F F F 8 R15 7 F F F F F E C Memory Memory 7FFFFFEC x x x x x x x x 7FFFFFEC x x x x x x x x 7FFFFFF0 x x x x x x x x 7FFFFFF0 x x x x x x x x 7FFFFFF4 x x x x x x x x 7FFFFFF4 8 0 0 0 0 0 0 0 7FFFFFF8 x x x x x x x x 7FFFFFF8 x x x x x x x x 7FFFFFFC x x x x x x x x 7FFFFFFC x x x x x x x x 80000000 x x x x x x x x
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.134 LEAVE (Leave Function) This instruction is used for stack frame release processing for high level languages.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: LEAVE Instruction bit pattern : 1001 1111 1001 0000 R14 7 F F F F F F 4 R14 8 0 0 0 R15 7 F F F F F E C R15 7 F F F F F F 8 Memory 0 0 0 0 Memory 7FFFFFEC x x x x x x x x 7FFFFFEC x x x x x x x x 7FFFFFF0 x x x x x x x x 7FFFFFF0 x x x x x x x x 7FFFFFF4 8 0 0 0 0 0 0 0 7FFFFFF4 8 0 0 0 0 0 0 0 7FFFFFF8 x x x x x x x x 7FFFFFF8 x x x x x x x x 7FFFFFFC x x x x x x x x 7FFFFFFC x x x x x x x x 80000000 x x x x x
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.135 XCHB (Exchange Byte Data) Exchanges the contents of the byte address indicated by "Rj" and those indicated by "Ri". The lower 8 bits of data originally at "Ri" are transferred to the byte address indicated by "Rj", and the data originally at "Rj" is extended with zeros and transferred to "Ri". The CPU will not accept hold requests between the memory read operation and the memory write operation of this instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example: XCHB @R1, R0 Instruction bit pattern : 1000 1010 0001 0000 R0 0 0 0 0 0 0 7 8 R0 0 0 0 0 0 0 F D R1 8 0 0 0 0 0 0 2 R1 8 0 0 0 0 0 0 2 Memory Memory 80000001 x x 80000001 x x 80000002 F D 80000002 7 8 80000003 x x 80000003 x x Before execution After execution 259
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 260
APPENDIX The appendix section includes lists of CPU instructions used in the FR family, as well as instruction map diagrams.
APPENDIX A Instruction Lists APPENDIX A Instruction Lists Appendix A includes a description of symbols used in instruction lists, plus the instruction lists. A.1 Symbols Used in Instruction Lists A.
APPENDIX A Instruction Lists A.1 Symbols Used in Instruction Lists This section describes symbols used in the FR family instruction lists. ■ Symbols Used in Instruction Lists ● Symbols in Mnemonic and Operation Columns • i4 ............. 4-bit immediate data, range 0 to 15 with zero extension, and –16 to –1 with minus extension • i8 ............. unsigned 8-bit immediate data, range 0 to 255 • i20 ........... unsigned 20-bit immediate data, range 00000H to FFFFFH • i32 ...........
APPENDIX A Instruction Lists ● Format Column A to F .......... format TYPE-A through F as described in Section "6.1 Instruction Formats". ● OP Column "OP" codes have the following significance according to the format type listed in the format column. • Format types A, C, D ..... 2-digit hexadecimal value represents 8-bit "OP" code. • Format type B ................ 2-digit hexadecimal value represents higher 4 bits of "OP" code, lower 4 bits "0". • Format type E ................
APPENDIX A Instruction Lists A.2 Instruction Lists The full instruction set of the FR family CPU is 165 instructions, consisting of the following sixteen types. These instructions are listed in Table A.2-1 through Table A.2-16.
APPENDIX A Instruction Lists Table A.2-2 Compare Instructions (3 Instructions) Mnemonic Format OP CYC A C C AA A8 A9 1 1 1 CMP Rj, Ri CMP #i4, Ri CMP2 #i4, Ri FLAG NZVC Operation CCCC CCCC CCCC Remarks Ri – Rj Ri – extu(i4) Ri – extn(i4) Zero extension Minus extension Table A.
APPENDIX A Instruction Lists Table A.
APPENDIX A Instruction Lists Table A.
APPENDIX A Instruction Lists Table A.
APPENDIX A Instruction Lists Table A.
APPENDIX A Instruction Lists Table A.
APPENDIX A Instruction Lists Table A.
APPENDIX A Instruction Lists Table A.
APPENDIX B Instruction Maps APPENDIX B Instruction Maps This appendix presents FR family instruction map and "E" format. B.1 Instruction Map B.
0 1 LD @(R15, udisp6),Ri LD @Rj,Ri 2 3 4 DMOVH @d9, DMOVH R13 R13, @d9 DMOVB @d8, DMOVB R13 R13, @d8 DMOV DMOV @d10,@–R15 @R15+,@d10 DMOV DMOV @d10,@R13+ @R13+,@d10 DMOVH @d9, DMOVH @R13+ @R13+, @d9 DMOVB DMOVB @d8, @R13+ @R13+, @d8 ENTER #u10 9 A B C D E F E format INT #u8 DMOV R13,@d10 E format DMOV @d10,R13 8 LDUB @Rj,Ri STB Ri,@Rj 6 7 LDUH @Rj,Ri STH Ri,@Rj 5 ST Ri,@Rj ST Ri, @(R15,ud6) LDUH STH Ri, @(R13,Rj), Ri @(R13,Rj) LDUB STB Ri, @(R13,Rj), Ri @(R13,Rj) 1 LD @
APPENDIX B Instruction Maps B.2 "E" Format This section shows "E" format for FR family CPU. ■ "E" Format Table B.
INDEX INDEX The index follows on the next page. This is listed in alphabetical order.
INDEX Index A ADD ADD (Add 4-bit Immediate Data to Destination Register)............................................... 73 ADD (Add Word Data of Source Register to Destination Register) ............................. 72 ADD2 (Add 4-bit Immediate Data to Destination Register)............................................... 74 Add Stack Pointer ADDSP (Add Stack Pointer and Immediate Data) ..........................................................
INDEX Bit Patterns Relation between Bit Patterns "Ri" and "Rj" and Register Values..................................... 64 BORH BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ......................... 112 BORL BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ......................... 110 Branch Relative Bcc (Branch Relative if Condition Satisfied) ...... 194 Bcc:D (Branch Relative if Condition Satisfied) ..........................................................
INDEX Examples of Programing Delayed Branching Instructions ........................................... 62 Overview of Branching with Delayed Branching Instructions ........................................... 58 Restrictions on Interrupts during Processing of Delayed Branching Instructions .............. 59 Destination Register ADD (Add 4-bit Immediate Data to Destination Register)............................................... 73 ADD (Add Word Data of Source Register to Destination Register) ..............
INDEX DMOVB (Move Byte Data from Register to Direct Address)............................................. 222 DMOVH DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address) .......................................................... 217 DMOVH (Move Half-word Data from Direct Address to Register)......................................... 215 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address) ............................................
INDEX Interlocking Produced by Reference to "R15" and General-purpose Registers after Changing the "S" Flag .......................................... 57 Overview of General-purpose Registers................ 15 Special Uses of General-purpose Registers ........... 15 H Hazards Overview of Register Hazards ............................. 56 I ILM Interrupt Level Mask Register (ILM: Bit 20 to bit 16) ............................................................
INDEX Precautionary Information for Use of "INT" Instructions........................................... 45 Time to Start of Trap Processing for "INT" Instructions........................................... 45 INTE "INTE" Instruction Operation.............................. 46 "PC" Values Saved for "INTE" Instruction Execution ............................................................ 46 INTE (Software Interrupt for Emulator) ............. 190 Overview of the "INTE" Instruction.....................
INDEX LDI:8 (Load Immediate 8-bit Data to Destination Register)............................................. 149 Load Multiple Registers LDM0 (Load Multiple Registers)....................... 246 LDM1 (Load Multiple Registers)....................... 248 Load Word Data LD (Load Word Data in Memory to Program Status Register)............................................. 157 LD (Load Word Data in Memory to Register) .................. 150, 151, 152, 153, 154, 155 LDRES (Load Word Data in Memory to Resource) ...
INDEX N NMI Relation of Step Trace Traps to "NMI" and External Interrupts.............................................. 47 No Operation NOP (No Operation) ........................................ 237 Non-delayed Branching Instructions Examples of Processing Non-delayed Branching Instructions........................................... 60 Overview of Branching with Non-delayed Branching Instructions...........................................
INDEX Interrupt Level Mask Register (ILM: Bit 20 to bit 16) ............................................................ 19 LD (Load Word Data in Memory to Program Status Register)............................................. 157 Note on PS Register............................................ 22 Overview of the Multiplication/Division Register ............................................................ 29 Overview of the Table Base Register....................
INDEX EORB (Exclusive Or Byte Data of Source Register to Data in Memory)................................. 104 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) ................ 102 MOV (Move Word Data in Source Register to Destination Register) ........... 178, 179, 181 MOV (Move Word Data in Source Register to Program Status Register) ..................... 182 OR (Or Word Data of Source Register to Data in Memory) ..............................................
INDEX System Stack Pointer Functions of the System Stack Pointer and User Stack Pointer ................................................. 28 System Stack Pointer (SSP),User Stack Pointer (USP) ............................................................ 27 T Table Base Register Overview of the Table Base Register.................... 23 Precautions Related to the Table Base Register ..... 24 Table Base Register Configuration....................... 24 Table Base Register Functions.............................
CM71-00101-5E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR Family 32-BIT MICROCONTROLLER INSTRUCTION MANUAL December 2007 the fifth edition Published FUJITSU LIMITED Edited Strategic Business Development Dept Electronic Devices
