FUJITSU SEMICONDUCTOR CM44-10136-1E CONTROLLER MANUAL 2 TM F MC -16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL
F2MCTM-16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL FUJITSU LIMITED
PREFACE ■ Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB90360 series has been developed as a general-purpose version of the F2MC-16LX family, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC). This manual explains the functions and operation of the MB90360 series for engineers who actually use the MB90360 series to design products. Please read this manual first.
CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. CHAPTER 11 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. CHAPTER 12 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. CHAPTER 13 16-Bit I/O TIMER This chapter explains the function and operation of the 16- bit I/O timer. CHAPTER 14 16-BIT RELOAD TIMER This chapter describes the functions and operation of the 16-bit reload timer.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/AF210/ AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation when the AF220/AF210/AF120/AF110 flash serial microcontroller programer from Yokogawa Digital Computer Corporation is used. CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function.
• • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information.
CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 CHAPTER 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.8 2.9 2.10 2.11 CPU ............................................................................................................ 27 Outline of the CPU ............................................................................................................................ Memory Space ............................................................................................................
CHAPTER 4 4.1 4.2 4.3 4.3.1 4.4 4.5 4.6 Overview of Delayed Interrupt Generation Module ........................................................................... Block Diagram of Delayed Interrupt Generation Module .................................................................. Configuration of Delayed Interrupt Generation Module .................................................................... Delayed interrupt request generate/cancel register (DIRR) ...............................................
CHAPTER 9 MEMORY ACCESS MODES .................................................................... 161 9.1 Outline of Memory Access Modes .................................................................................................. 9.1.1 Mode Pins .................................................................................................................................. 9.1.2 Mode Data ..............................................................................................................
13.5 13.6 13.7 13.8 Explanation of Operation of 16-bit Free-run Timer ......................................................................... Explanation of Operation of Input Capture ..................................................................................... Precautions when Using 16-bit I/O Timer ....................................................................................... Program Example of 16-bit I/O Timer ...........................................................................
CHAPTER 17 DTP/EXTERNAL INTERRUPTS .............................................................. 313 17.1 Overview of DTP/External Interrupt ................................................................................................ 17.2 Block Diagram of DTP/External Interrupt ........................................................................................ 17.3 Configuration of DTP/External Interrupt .......................................................................................... 17.
20.4.2 LIN-UART Serial Mode Register (SMR) .................................................................................... 20.4.3 Serial Status Register (SSR) ..................................................................................................... 20.4.4 Reception and Transmission Data Register (RDR/TDR) ........................................................... 20.4.5 Extended Status/Control Register (ESCR) ................................................................................
21.4.20 Reception Interrupt Enable Register (RIER) ............................................................................. 21.4.21 Acceptance Mask Select Register (AMSR) ............................................................................... 21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) .......................................................... 21.4.23 Message Buffers ...................................................................................................................
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S)SERIAL PROGRAMMING CONNECTION .......................................................................................... 553 25.1 25.2 25.3 25.4 25.5 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) ... Example of Serial Programming Connection (User Power Supply Used) ...................................... Example of Serial Programming Connection (Power Supplied from Programmer) ........................
CHAPTER 1 OVERVIEW The MB90360 Series is a family member of the F2MC16LX micro controllers. 1.1 Overview of MB90360 1.2 Block Diagram of MB90360 series 1.3 Package Dimensions 1.4 Pin Assignment 1.5 Pin Functions 1.6 Input-Output Circuits 1.
CHAPTER 1 OVERVIEW 1.1 Overview of MB90360 The MB90360 Series is a 16-bit microcontroller designed for automotive applications and contains CAN function, capture, compare timer, A/D converter, and so on.
CHAPTER 1 OVERVIEW ● CPU-independent automatic data transfer function Extended intelligent I/O service (EI2OS): Maximum 16 channels ● Lower-power consumption (standby) modes • Sleep mode (stops CPU clock) • Timebase timer mode (operates only oscillation clock and subclock, timebase timer and watch timer) • Watch mode (product without S-suffix operates only subclock and watch timer) • Stop mode (stops oscillation clock and subclock) • CPU intermittent operation mode ● Process CMOS Technology ● I/O ports
CHAPTER 1 OVERVIEW ● Delayed interrupt generation module Generates interrupt request for task switching ● 8-/10-bit A/D converter: 16 channels • 8-bit and 10-bit resolutions • Start by external trigger input • Conversion time: 3 µs (including sampling time at 24-MHz machine clock frequency) ● Program patch function Detects address match for six address pointers ● Low voltage/CPU operation detection reset function (product with T-suffix) • Detects low voltage (4.0 V ± 0.
CHAPTER 1 OVERVIEW ■ Product overview Table 1.1-1 Product Overview (1/2) Features MB90362 MB90362T MB90362S CPU MB90362TS MB90V340 A-101 MB90V340 A-102 F2MC-16LX CPU System clock pin PLL clock multiplier (✕1, ✕2, ✕3, ✕4, ✕6, 1/2 when PLL stops) Minimum instruction execution time: 42 ns (4 MHz osc.
CHAPTER 1 OVERVIEW Table 1.1-2 Product Overview (2/2) Features MB90367 MB90367T MB90367S CPU MB90367TS MB90V340 A-103 MB90V340 A-104 F2MC-16LX CPU System clock pin PLL clock multiplier (✕1, ✕2, ✕3, ✕4, ✕6, 1/2 when PLL stops) Minimum instruction execution time: 42 ns (4 MHz osc.
CHAPTER 1 OVERVIEW ■ Features Table 1.
CHAPTER 1 OVERVIEW Table 1.1-3 MB90360 Features (2/2) Features CAN interface MB90F362/T(S), MB90362/T(S) MB90F367/T(S), MB90367/T(S) MB90V340A-101, MB90V340A-102 MB90V340A-103, MB90V340A-104 3 channels 1 channel Conforms to CAN Specification Version 2.
CHAPTER 1 OVERVIEW 1.2 Block Diagram of MB90360 series Figure 1.2-3 shows a block diagram of the MB90360. ■ Block Diagram of Evaluation Chip Figure 1.
CHAPTER 1 OVERVIEW Figure 1.
CHAPTER 1 OVERVIEW ■ Block Diagram of Flash/Mask ROM Version Figure 1.
CHAPTER 1 OVERVIEW 1.3 Package Dimensions MB90360 series has a package. Note that the dimensions show below are reference dimensions. For formal dimensions of each package, contact us. ■ Package Dimensions Figure 1.3-1 shows the package dimensions of LQFP-48 type. Figure 1.3-1 Package Dimensions of LQFP-48 Type 48-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 7 × 7 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.
CHAPTER 1 OVERVIEW 1.4 Pin Assignment This section shows the pin assignments for the MB90360 series. ■ Pin assignment (LQFP-48) Figure 1.4-1 shows the pin assignments of LQFP-48 type. Figure 1.
CHAPTER 1 OVERVIEW 1.5 Pin Functions Table 1.5-1 describes the pin functions of the MB90360 series. ■ Pin Functions Table 1.5-1 Pin Description (1/3) Pin number Pin name Circuit type Functional description 1 AVCC I VCC power input pin for analog circuit 2 AVR - Power (Vref+) input pin for A/D converter. The power supply should not be input VCC exceeding. 3 to 8 P60 to P65 H General-purpose I/O port AN0 to AN5 9 to 10 11 12 to 14 P66, P67 Analog input pin for A/D converter.
CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (2/3) Pin number Pin name Circuit type Functional description 26 C I Capacity pin for stabilizing power supply. It should be connected to higher than or equal to 0.1 µF ceramic capacitor. 27 X0 A Oscillation input pin 28 X1 A Oscillation output pin 29 to 32 P24 to P27 G General-purpose I/O port The register can be set to select whether to use pull-up register. This function is enabled in single-chip mode.
CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (3/3) Pin number 45 Pin name P44 Circuit type F FRCK0 46, 47 48 16 Functional description General-purpose I/O port (I/O circuit type of P44 is different from that of MB90V340A.
CHAPTER 1 OVERVIEW 1.6 Input-Output Circuits Table 1.6-1 lists the input-output circuits. ■ Input-output Circuits Table 1.6-1 I/O Circuit Types (1/4) Type A Circuit X1 Remarks Xout Oscillation circuit High-speed oscillation feedback resistor = approx. 1 MΩ X0 Standby control signal B X1A Xout Oscillation circuit Low-speed oscillation feedback resistor = approx.
CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (2/4) Type Circuit Remarks E CMOS hysteresis input pin Pull-up resister value: approx.
CHAPTER 1 OVERVIEW Table 1.
CHAPTER 1 OVERVIEW Table 1.
CHAPTER 1 OVERVIEW 1.7 Handling Device This section explains notes on handling the MB90360 series. ■ Handling the Device ● Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage.
CHAPTER 1 OVERVIEW ● Using external clock To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open. Figure 1.7-1 Using External Clock MB90360 series X0 (X0A) Open X1 (X1A) ● Precautions for when not using a sub clock signal If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
CHAPTER 1 OVERVIEW Figure 1.7-2 Power Supply Pins (VCC/VSS) Vcc Vss Vcc Vss Vss Vcc MB90360 series Vcc Vss Vss Vcc ● Pull-up/down resistors The MB90360 Series does not support internal pull-up/down resistors (except Port2: programmable pull-up resistors). Use pull-up/down handling where needed. ● Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations.
CHAPTER 1 OVERVIEW ● Notes on Energization To prevent malfunction of the internal voltage regulator, supply voltage profile while turning on the power supply should be slower than 50 µs from 0.2 V to 2.7 V. ● Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized.
CHAPTER 1 OVERVIEW ● Flash security Function The security bit is located in the area of the flash memory. If protection code 01H is written in the security bit, the flash memory is in the protected state by security. Therefore please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security bit.
CHAPTER 1 OVERVIEW 26
CHAPTER 2 CPU This chapter explains the CPU. 2.1 Outline of the CPU 2.2 Memory Space 2.3 Memory Map 2.4 Linear Addressing 2.5 Bank Addressing Types 2.6 Multi-byte Data in Memory Space 2.7 Registers 2.8 Register Bank 2.9 Prefix Codes 2.10 Interrupt Disable Instructions 2.
CHAPTER 2 CPU 2.1 Outline of the CPU The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. ■ Outline of the CPU In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator.
CHAPTER 2 CPU 2.2 Memory Space An F2MC-16LX CPU has a 16M bytes memory space. All data program input and output managed by the F2MC-16LX CPU are located in this 16M bytes memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. ■ Outline of CPU Memory Space Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map. Figure 2.
CHAPTER 2 CPU ■ ROM area ● Vector table area (address: FFFC00H to FFFFFFH) This area is used as a vector table for reset/interrupt and CALLV vector. This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address. ● Program area (address: FF0000H to FFFBFFH) ROM is built in as an internal program area. The size of internal ROM differs for each model.
CHAPTER 2 CPU ■ Address generation types The F2MC-16LX has the following 2 addressing modes: ● Linear addressing An entire 24-bit address is specified by an instruction. ● Bank addressing. The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction.
CHAPTER 2 CPU 2.3 Memory Map The memory map of the MB90360 Series is shown in Figure 2.3-1 . ■ Memory Map The ROM data in the high-order portion of FF-bank can be seen as an image in the higher 00-bank in order to support the small model C compiler. Since the low-order 16 bits are identical, this part of the ROM data can be referred without using the far specification in the pointer declaration. For example, when 00C000H is accessed, the contents of ROM at FFC000H are read.
CHAPTER 2 CPU 2.4 Linear Addressing There are 2 types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32bit general-purpose register value as the address. ■ 24-bit Operand Specification Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example of 32-bit register indirect specification. Figure 2.
CHAPTER 2 CPU 2.5 Bank Addressing Types In the bank method, the 16M bytes space is divided into 256 for 64K bytes banks. The following 5 bank registers are used to specify the banks corresponding to each space: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional bank register (ADB) ■ Bank Addressing Types ● Program bank register (PCB) The 64K bytes bank specified by the PCB is called a program (PC) space.
CHAPTER 2 CPU Table 2.5-1 Default Space Default space Program space Addressing mode PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.5-1 is an example of a memory space divided into register banks. Figure 2.
CHAPTER 2 CPU 2.6 Multi-byte Data in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is inputted immediately after the low-order bits are written, the highorder bits might not be written. ■ Multi-byte Data Allocation in Memory Space Figure 2.6-1 is a diagram of multi-byte data configuration in memory.
CHAPTER 2 CPU 2.7 Registers The F2MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The general-purpose registers share the CPU address space with RAM. The general-purpose registers are the same as the special registers in that they can be accessed without using an address.
CHAPTER 2 CPU Figure 2.
CHAPTER 2 CPU ■ General-purpose registers The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.7-2 .
CHAPTER 2 CPU 2.7.1 Accumulator (A) The accumulator (A) register consists of 2 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) During 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16bit data processing mode or for byte processing in 8-bit data processing mode (see Figure 2.7-3 and Figure 2.7-4 ).
CHAPTER 2 CPU 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) The USP and SSP registers are used by stack instructions. The USP register is enabled when the S flag in the processor status register is “0”, and the SSP register is enabled when the S flag is “1” (see Figure 2.7-5 ).
CHAPTER 2 CPU 2.7.3 Processor Status (PS) The PS register consists of the bits controlling the CPU operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.7-6 , the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The ILM indicates the start address of a register bank.
CHAPTER 2 CPU ● T: Sticky bit flag: 1 is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero. ● N: Negative flag: The N flag is set when the MSB of the operation result is "1", and is otherwise cleared.
CHAPTER 2 CPU ■ Interrupt level mask register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1 ). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value.
CHAPTER 2 CPU 2.7.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access. ■ Program Counter (PC) Figure 2.7-10 shows the program counter.
CHAPTER 2 CPU 2.8 Register Bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers. RL0 to RL3 are used as the linear pointer that directly accesses entire space. ■ Register Bank Table 2.8-1 lists the functions of the registers. Table 2.
CHAPTER 2 CPU 2.8-1 . DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an instruction. Figure 2.
CHAPTER 2 CPU 2.9 Prefix Codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank Select Prefix The memory space used for accessing data is determined for each addressing mode.
CHAPTER 2 CPU ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ● RETI SSB is used regardless of the prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value.
CHAPTER 2 CPU ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction.
CHAPTER 2 CPU 2.10 Interrupt Disable Instructions Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - SPB - OR CCR,#imm8 - AND CCR,#imm8 - ADB - CMR - POPW PS - NCC - DTB ■ Interrupt Disable Instructions If a valid hardware interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. For details, see Figure 2.10-1 . Figure 2.
CHAPTER 2 CPU 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Set "00H" in the bank register before using the "DIV A, Ri" and "DIVW A, RWi" instructions. ■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Table 2.
CHAPTER 2 CPU Example: If "DIV A,R0" is executed with DTB = "053H" and RP = "03H", the address of R0 is "0180H" + RP ("03H") × "10H" + "08H" (R0 corresponding address) = "0001B8H". Since the data bank register (DTB) is specified by "DIV A,R0" as the bank register, the remainder is stored in address "05301B8H", which was obtained by adding the bank address "053H". Note: For information about the bank register and Ri and RWi registers, see "2.7 Registers".
CHAPTER 2 CPU 54
CHAPTER 3 INTERRUPTS This chapter explains the interrupts and function and operation of the extended intelligent I/O service in the MB90360 series. 3.1 Outline of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts 3.7 Extended Intelligent I/O Service (EI2OS) 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) 3.
CHAPTER 3 INTERRUPTS 3.1 Outline of Interrupts The F2MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs.
CHAPTER 3 INTERRUPTS ■ Software Interrupts Interrupts requested by executing the INT instruction are software interrupts. An interrupt request by the INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by executing the INT instruction. No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are suspended. Figure 3.
CHAPTER 3 INTERRUPTS ■ Exceptions Exception processing is basically the same as interrupt processing. When an exception is detected between instructions, ordinary processing is suspended, and exception processing is performed. In general, exception processing occurs as a result of an unexpected operation. Therefore, use exception processing for debugging programs or for activating recovery software in an emergency.
CHAPTER 3 INTERRUPTS 3.2 Interrupt Vector An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine. Interrupt vectors are allocated between addresses FFFC00H and FFFFFFH as shown in Table 3.2-1 . ■ Interrupt Vector Table 3.
CHAPTER 3 INTERRUPTS Table 3.
CHAPTER 3 INTERRUPTS 3.3 Interrupt Control Registers (ICR) The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function.
CHAPTER 3 INTERRUPTS Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels ILM2 ILM1 ILM0 Level 0 0 0 0 (strongest) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (weakest) 1 1 1 7 (no interrupt) [bit 11, bit 3] ISE (extended intelligent I/O service enable bits) The ISE bit is readable and writable. In response to an interrupt request, EI2OS is activated when '1' is set in the ISE bit and an interrupt sequence is activated when '0' is set in the ISE bit.
CHAPTER 3 INTERRUPTS [bit 15 to bit 12, bit 7 to bit 4] ICS 3 to ICS 0 (extended intelligent I/O service channel select bits) ICS3 to ICS0 are write-only bits. These bits specify the EI2OS channel. The values set in these bits determined the extended intelligent I/O service descriptor addresses in memory, which is explained later. The ICS bits are initialized to "0000B" by a reset. Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and descriptor addresses. Table 3.
CHAPTER 3 INTERRUPTS [bit 13, bit 12, bits 5, bit 4] S0 and S1 (extended intelligent I/O service status) S0 and S1 are read-only bits. The values set in these bits indicate the end condition of EI2OS. These bits are initialized to '00' upon a reset. Table 3.3-3 shows the relationship between the S bits and the end conditions. Table 3.
CHAPTER 3 INTERRUPTS 3.4 Interrupt Flow Figure 3.4-1 shows the interrupt flow. ■ Interrupt Flow Figure 3.
CHAPTER 3 INTERRUPTS Figure 3.
CHAPTER 3 INTERRUPTS 3.5 Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function.
CHAPTER 3 INTERRUPTS 3.5.1 Hardware Interrupt Operation An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU. The interrupt request flag is set when an event that is unique to the internal resource occurs.
CHAPTER 3 INTERRUPTS 3.5.2 Occurrence and Release of Hardware Interrupt Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to release of the interrupt request in an interrupt processing program. ■ Occurrence and Release of Hardware Interrupt Figure 3.
CHAPTER 3 INTERRUPTS The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below. See Table 3.5-1 for the cycle count compensation value. Interrupt start: 24 + 6 × (Table 3.3-2 machine cycles) Interrupt return: 15 + 6 × (Table 3.3-2 machine cycles) RETI instruction Table 3.
CHAPTER 3 INTERRUPTS 3.5.3 Multiple interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. This is intended to prevent the CPU from operating falsely because of an interrupt request issued while an interrupt control register for a resource is being updated. If an interrupt occurs during interrupt processing, a higher-level interrupt is processed first. ■ Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts.
CHAPTER 3 INTERRUPTS 3.6 Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.
CHAPTER 3 INTERRUPTS Figure 3.6-1 Occurrence and Release of Software Interrupt (1) PS F2MC-16LX bus Register file I (2) Micro code F2MC-16LX • CPU S B unit IR Queue Fetch PS I ILM IR : Processor status : Interrupt enable flag : Interrupt level mask register : Instruction register B unit : Bus interface unit Save Instruction bus RAM (1) The software interrupt instruction is executed.
CHAPTER 3 INTERRUPTS 3.7 Extended Intelligent I/O Service (EI2OS) The EI2OS function, a kind of hardware interrupt operation, automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such processing, but EI2OS enables data transfer to be performed like DMA (direct memory access).
CHAPTER 3 INTERRUPTS Figure 3.7-1 Outline of Extended Intelligent I/O Service Memory space by IOA I/O register ··· ··· ··· ··· ··· I/O register Peripheral CPU Interrupt request ISD by ICS Interrupt control register Interrupt controller by BAP I/O requests transfer. Interrupt controller selects descriptor. Buffer by DCT Transfer source and destination are read from descriptor. Data is transferred between I/O and memory. Note: • The area that can be specified by IOA is between 000000H and 00FFFFH.
CHAPTER 3 INTERRUPTS 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100H and 00017FH in internal RAM and consists of the following items: • Data transfer control data • Status data • Buffer address pointer ■ Extended Intelligent I/O Service Descriptor (ISD) Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor. Figure 3.
CHAPTER 3 INTERRUPTS ■ I/O register address pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000H and 00FFFFH can be specified. Figure 3.7-4 is a diagram of the IOA configuration. Figure 3.
CHAPTER 3 INTERRUPTS 3.7.2 EI2OS Status Register (ISCS) This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed. ■ EI2OS Status Register (ISCS) Figure 3.7-5 is a diagram of the ISCS configuration. Be sure to write "0" in bit 7 to bit 5 of ISCS.
CHAPTER 3 INTERRUPTS 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) Figure 3.8-1 is a diagram of the EI2OS operation flow. Figure 3.8-2 is a diagram of the EI2OS use procedure. ■ EI2OS Operation Flow Figure 3.
CHAPTER 3 INTERRUPTS Figure 3.8-2 EI2OS Use Flow Processing by EI2OS Processing by CPU EI2OS initialization (Interrupt request) Normal termination AND (ISE=1) JOB execution Data transfer Count out or interrupt generation by end request from resource Setting of extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI2OS execution time for each flow is described below. ● When data transfer continues (when the stop condition is not satisfied) (Figure 3.
CHAPTER 3 INTERRUPTS Table 3.8-2 Data Transfer Compensation Values for EI2OS Execution Time Internal access I/O address pointer Buffer address pointer Internal access B/E O B/E 0 +2 O +2 +4 B: Byte data transfer E: Even address word transfer O: Odd address word transfer Table 3.
CHAPTER 3 INTERRUPTS 3.9 Exceptions The F2MC-16LX performs exception processing when the following event occurs: ■ Execution of an Undefined Instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE This chapter explains the functions and operations of the delayed interrupt generation module. 4.1 Overview of Delayed Interrupt Generation Module 4.2 Block Diagram of Delayed Interrupt Generation Module 4.3 Configuration of Delayed Interrupt Generation Module 4.4 Explanation of Operation of Delayed Interrupt Generation Module 4.5 Precautions when Using Delayed Interrupt Generation Module 4.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.1 Overview of Delayed Interrupt Generation Module The delayed interrupt generation module generates the interrupt for task switching. The hardware interrupt request can be generated/cancelled by software. ■ Overview of Delayed Interrupt Generation Module By using the delayed interrupt generation module, a hardware interrupt request can be generated or cancelled by software. Table 4.1-1 shows the overview of the delayed interrupt generation module. Table 4.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.2 Block Diagram of Delayed Interrupt Generation Module The delayed interrupt generation module consists of the following blocks: • Interrupt request latch • Delayed interrupt request generate/cancel register (DIRR) ■ Block Diagram of Delayed Interrupt Generation Module Figure 4.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.3 Configuration of Delayed Interrupt Generation Module This section lists registers and reset values in the delayed interrupt generation module. ■ List of Registers and Reset Values Figure 4.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.3.1 Delayed interrupt request generate/cancel register (DIRR) The delayed interrupt request generate/cancel register (DIRR) generates or cancels a delayed interrupt request. ■ Delayed Interrupt Request Generate/cancel Register (DIRR) Figure 4.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.4 Explanation of Operation of Delayed Interrupt Generation Module The delayed interrupt generation module has a function for generating or canceling an interrupt request by software. ■ Explanation of Operation of Delayed Interrupt Generation Module Using the delayed interrupt generation module requires the setting shown in Figure 4.4-1 . Figure 4.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.5 Precautions when Using Delayed Interrupt Generation Module This section explains the precautions when using the delayed interrupt generation module. ■ Precautions when Using Delayed Interrupt Generation Module • The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to "0" within the interrupt processing routine.
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE 4.6 Program Example of Delayed Interrupt Generation Module This section gives a program example of the delayed interrupt generation module. ■ Program Example of Delayed Interrupt Generation Module ● Processing specification The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to generate a delayed interrupt request and performs task switching.
CHAPTER 5 CLOCKS This chapter explains the clocks used by MB90360 series microcontrollers. 5.1 Clocks 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Register (CKSCR) 5.4 PLL/Subclock Control Register (PSCCR) 5.5 Clock Mode 5.6 Oscillation Stabilization Wait Interval 5.
CHAPTER 5 CLOCKS 5.1 Clocks The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. The clock generated by the clock generation block is called the machine clock. One cycle of machine clock is called one machine cycle. The clock to be supplied from a high-speed oscillator is called an oscillation clock, and the 2-frequency division of the oscillation clock is called a main clock.
CHAPTER 5 CLOCKS ● Machine clock The machine clock controls the operation of the CPU and peripheral functions. One cycle of machine clock is regarded as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock, sub-clock, and five types of PLL clock. Note: When the operating voltage is 5 V, the oscillation clock can be between 3 MHz and 16 MHz. When an external clock source is used, its frequency can be between 3 MHz and 24 MHz.
CHAPTER 5 CLOCKS ■ Clock Supply Map Since the machine clock generated in the clock generation block is supplied as the clock that controls the operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions is affected by switching between the main clock, the PLL clock and the subclock (clock mode) and by a change in the PLL clock multiplication ratio.
CHAPTER 5 CLOCKS 5.2 Block Diagram of the Clock Generation Block The clock generation block consists of five blocks: • System clock generation circuit/sub-clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • PLL/sub-clock control register (PSCCR) • Oscillation stabilization wait interval selector ■ Block Diagram of the Clock Generation Block Figure 5.2-1 shows a block diagram of the clock generation block.
CHAPTER 5 CLOCKS ● Oscillation clock generation circuit This circuit generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external clock to the high-speed oscillation pins. ● Sub-clock generation circuit This circuit generates a sub clock (SCLK) by connecting an oscillator or inputting an external clock to the low-speed oscillation pins (X0A, X1A).
CHAPTER 5 CLOCKS 5.2.1 Register of Clock Generation Block This section explains the register of the clock generation block. ■ Clock Selection Register and List of Reset Value Figure 5.
CHAPTER 5 CLOCKS 5.3 Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to switch among the main clock, PLL clocks and subclock, also used to select an oscillation stabilization wait interval and a PLL clock multiplier. ■ Configuration of the Clock Selection Register (CKSCR) Figure 5.
CHAPTER 5 CLOCKS Table 5.3-1 Functions of Clock Selection Register (CKSCR) (1/2) Bit name Function bit15 SCM: The bit indicates the main clock or subclock currently selected as the machine clock. Sub clock operation When the sub clock operation flag bit (CKSCR: SCM) is "0" and the sub clock select bit flag bit (CKSCR: SCS) is "1", it indicates that the machine clock is currently switching from subclock to main clock.
CHAPTER 5 CLOCKS Table 5.3-1 Functions of Clock Selection Register (CKSCR) (2/2) Bit name Function bit10 MCS: This bit indicates the main clock or PLL clock to be selected as the machine clock. PLL clock select bit When the machine clock is switched from the main clock to the PLL clock (CKSCR: MCS = 1 → 0), the clock mode changes from main clock mode to PLL clock mode after the PLL clock oscillation stabilization wait time is generated.The timebase timer is cleared automatically.
CHAPTER 5 CLOCKS 5.4 PLL/Subclock Control Register (PSCCR) PLL/Subclock control register selects the PLL multiplication rate and subclock division rate. This register is write only. Read value of all bits is set to "1". ■ Configuration of the PLL/Subclock Control Register (PSCCR) Figure 5.4-1 shows the configuration of the PLL/Subclock control register (PSCCR). Table 5.4-1 shows the function of each bit in the PLL/subclock control register (PSCCR). Figure 5.
CHAPTER 5 CLOCKS Table 5.4-1 Functional Description of Each Bit in the PLL/subclock Control Register (PSCCR) Bit name Function bit15 to bit12 Unused These bits are not used. Writing to these bits has no effect to operation. Read value is always "1". bit11 Reserved bit Always write "0" to this bit. Read value is always "1". bit10 SCDS: Subclock division selection bit The division ratio of the subclock is selected. When "0" is written to this bit, 4 division is selected.
CHAPTER 5 CLOCKS 5.5 Clock Mode Three clock modes are provided: main clock mode, PLL clock mode and sub-clock mode. ■ Clock Mode ● Main clock mode In main clock mode, a clock with 2-frequency division of the clock generated by connecting on oscillator or by inputting from external to the high-speed oscillation pins (X0, X1) is used.
CHAPTER 5 CLOCKS ● Transition from sub-clock mode to main clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “0” to “1” in sub-clock mode, switching from the sub-clock to the main clock occurs after the main clock oscillation stabilization wait interval. ● Transition from PLL clock mode to sub-clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “1” to “0” in PLL clock mode, switching from the PLL clock to the sub-clock occurs.
CHAPTER 5 CLOCKS Figure 5.5-1 shows the status change caused by machine clock switching. Figure 5.
CHAPTER 5 CLOCKS (1) (2) Write "0" to MCS bit Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 00B& CS2= 0 (3) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 01B& CS2= 0 (4) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 0 (5) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 11B& CS2= 0 (6) Termination of PLL clock oscillation stabilization wait time & CS1, CS0= 10B& CS2= 1 (7) (8) (9) (1
CHAPTER 5 CLOCKS 5.6 Oscillation Stabilization Wait Interval When the power is turned on during the oscillation clock is stopped or when stop mode is released, a time until the oscillation clock stabilizes (oscillation stabilization wait time is required immediately after oscillation starts. Also, the oscillation stabilization wait time is required when the clock mode is switched from main clock to PLL clock, main clock to sub-clock, sub-clock to main clock, and sub-clock to PLL clock.
CHAPTER 5 CLOCKS 5.7 Connection of an Oscillator or an External Clock to the Microcontroller The MB90360 series microcontroller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the microcontroller. ■ Connection of an Oscillator or an External Clock to the Microcontroller ● Example of connecting a crystal or ceramic oscillator to the microcontroller Figure 5.
CHAPTER 6 CLOCK SUPERVISOR This chapter explains the function and the operation of the clock supervisor. Only the product with built-in clock supervisor of the MB90360 series is valid to this function. 6.1 Overview of Clock Supervisor 6.2 Block Diagram of Clock Supervisor 6.3 Clock Supervisor Control Register (CSVCR) 6.
CHAPTER 6 CLOCK SUPERVISOR 6.1 Overview of Clock Supervisor The clock supervisor checks the oscillation of the main clock or a sub-clock (without "S" suffix product). When the main clock or a sub-clock stops due to some breakdowns, the control circuit of the clock supervisor switches the clock source to built-in CR oscillation clock, sets the detection flag, and generates reset. ■ Overview of Clock Supervisor The clock supervisor checks the oscillation of the main clock or the sub-clock.
CHAPTER 6 CLOCK SUPERVISOR 6.2 Block Diagram of Clock Supervisor The clock Supervisor is composed of the following block: • Main clock supervisor • Sub clock supervisor • Control circuit • Clock supervisor control register (CSVCR) • Main clock selector • Sub clock selector • CR oscillation circuit ■ Block Diagram of Clock Supervisor Figure 6.2-1 shows the block diagram of clock supervisor. Figure 6.
CHAPTER 6 CLOCK SUPERVISOR ● Main clock supervisor The oscillation of the main oscillation clock (HCLK) is supervised by using the clock from the CR oscillation circuit as a clock source. ● Sub clock supervisor The oscillation of the sub oscillation clock (SCLK) is supervised by using the clock from the CR oscillation circuit as a clock source.
CHAPTER 6 CLOCK SUPERVISOR 6.3 Clock Supervisor Control Register (CSVCR) This register switches main clock/sub clock/PLL clock, and selects the oscillation stabilization wait time and PLL clock multiplication rate. ■ Clock Supervisor Control Register (CSVCR) Figure 6.
CHAPTER 6 CLOCK SUPERVISOR Bit name Function bit7 SCKS Sub clock select This bit permits built-in CR oscillation clock to be used as a sub-clock. Only "S" suffix product is valid to this function. "1": It is possible to change to the sub clock mode with built-in CR oscillation clock. "0": It is not possible to change to the sub clock mode. This bit is initialized to "0" by power-on reset, external reset, or low voltage detection reset in "T" suffix product.
CHAPTER 6 CLOCK SUPERVISOR 6.4 Operating Mode of Clock Supervisor This section explains all the operating modes of the Clock Supervisor. ■ Operating Mode in Initialized State The CR oscillation circuit, the main clock supervisor and the sub-clock supervisor are enabled before the clock supervisor control register (CSVCR) is set by the user program. • After power-on reset or reset of the low voltage detection, the CR oscillation circuit is enabled with "T" suffix product.
CHAPTER 6 CLOCK SUPERVISOR • The sub-clock supervisor is operated by setting SSVE(CSVCR:bit2) to 1. Please note the programming of software to do after 10 µs or more has passed since the CR oscillation circuit was set enable. ■ Sub-clock Mode The main clock supervisor automatically becomes disable at the sub-clock mode. The content of enable bit MSVE never changes. If the main clock was lost after oscillation stability waiting time of 211/HCLK (about 0.
CHAPTER 6 CLOCK SUPERVISOR ■ Reset Check By Clock Supervisor To check whether reset was executed by the clock supervisor, the WDTC register is read with software and the reset factor is checked. When ERSR (bit4 of WDTC) is set, the factor is a reset from an external terminal or a reset by the clock supervisor (include low voltage detection/CPU operating detection reset in "T" suffix products).
CHAPTER 6 CLOCK SUPERVISOR 118
CHAPTER 7 RESETS This chapter describes resets for the MB90360-series microcontrollers. 7.1 Resets 7.2 Reset Cause and Oscillation Stabilization Wait Times 7.3 External Reset Pin 7.4 Reset Operation 7.5 Reset Cause Bits 7.
CHAPTER 7 RESETS 7.1 Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins processing at the address indicated by the reset vector.
CHAPTER 7 RESETS stabilization wait time has elapsed, the reset is executed. ● External reset An external reset is generated by the L level input to an external reset pin (RST pin). The minimum required period of the L level is at least 500 ns. Reset operation is performed after oscillation stabilization wait time elapses. Note: If the reset cause is generated during a write operation, the CPU waits for the reset to be cleared after completion of the instruction only for reset requests via the RST pin.
CHAPTER 7 RESETS ● CPU operation detection reset The CPU operation detection reset is 20-bit counter that the source oscillation is count-locked. If the CL bit of the low voltage/CPU operation detection reset is not cleared within a specified time after activation, the reset is generated. The oscillation stabilization wait time is not required for the CPU operation detection reset. ● Clock supervisor reset When the failure of the main clock/subclock is detected, the clock supervisor reset is generated.
CHAPTER 7 RESETS 7.2 Reset Cause and Oscillation Stabilization Wait Times The MB90360 series has seven reset causes. The oscillation stabilization wait time for a reset depends on the reset cause. ■ Reset Causes and oscillation Stabilization Wait Times Table 7.2-1 summarizes reset causes and oscillation stabilization wait times. Table 7.
CHAPTER 7 RESETS Figure 7.2-1 Oscillation Stabilization Wait Times at a Power-on Reset Vcc 215/HCLK 215/HCLK CLK CPU operation Stabilization wait time of voltage step-down circuit Oscillation stabilization wait time Note: Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several milliseconds to some tens of milliseconds, until stabilization at a natural frequency is attained after starts oscillation.
CHAPTER 7 RESETS 7.3 External Reset Pin The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an L level signal generates an internal reset. For the MB90360-series, resets are generated in synchronization with the CPU operating clock. However, initialization of external pin is asynchronous with the CPU operating clock. ■ Block Diagrams of the External Reset Pin ● Block diagram of the external reset pin Figure 7.
CHAPTER 7 RESETS 7.4 Reset Operation When the reset signal is inactivated, the reset vector and mode data is fetched from the predetermined locations depending on the setting of the mode pins. This operation, the mode fetch, then defines the operation mode of the CPU and the start address of the first instruction. For the power on reset, reset from the stop mode or sub-clock mode, the mode fetch is performed after the oscillation stabilization wait time is elapsed. ■ Overview of Reset Operation Figure 7.
CHAPTER 7 RESETS ■ Mode Fetch When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from "FFFFDCH" to "FFFFDFH". The CPU outputs these addresses to the bus immediately after the reset is cleared and then fetches the reset vector and mode data. Using mode fetching, the CPU can begin processing at the address indicated by the reset vector. Figure 7.
CHAPTER 7 RESETS 7.5 Reset Cause Bits A reset cause can be identified by reading the watchdog timer control register (WDTC). ■ Reset Cause Bits As shown in Figure 7.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC). If the cause of a reset must be identified after the reset has been cleared, the value read from the WDTC should be processed by the software and a branch made to the appropriate program.
CHAPTER 7 RESETS ■ Correspondence between reset cause bits and reset causes Figure 7.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See “Watchdog timer control register (WDTC)” in "12.1 Overview of Watchdog Timer", for details. Figure 7.
CHAPTER 7 RESETS ■ Status of Reset Cause Bit and Low Voltage Detection Bit Figure 7.5-3 Status of Reset Cause Bit and Low Voltage Detection Bit Flag status at power-on Bit clear Flag status at low voltage Bit detection (4V) clear Vcc=4V Vcc PONR bit (power-on) (1) 1 → (2) 0 → (3) 0 → (4) 0 ERST bit (external reset input, CPU operation detection, or LVRF = 1) 1 or 0 → 0 → 1 → 0 LVRF bit* (low voltage detection 4V ± 0.
CHAPTER 7 RESETS ■ Notes about Reset Cause Bits ● Multiple reset causes generated at the same time When multiple reset causes are generated at the same time, the corresponding reset cause bits of the watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are both set to "1".
CHAPTER 7 RESETS 7.6 Status of Pins in a Reset This section describes the status of pins when a reset occurs. ■ Status of Pins during a Reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0). About status of each pins during reset, please see "8.7 Status of Pins in Standby Mode and during Hold and Reset". ● When internal vector mode has been set: (MD2 to MD0 = "011B") All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
CHAPTER 8 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of MB90360 series microcontrollers. 8.1 Overview of Low-Power Consumption Mode 8.2 Block Diagram of the Low-Power Consumption Control Circuit 8.3 Low-Power Consumption Mode Control Register (LPMCR) 8.4 CPU Intermittent Operation Mode 8.5 Standby Mode 8.6 Status Change Diagram 8.7 Status of Pins in Standby Mode and during Hold and Reset 8.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ■ Clock Mode ● PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. ● Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Timebase timer mode The timebase timer mode operates the oscillation clock (HCLK), sub-clock (SCLK), timebase timer, watch timer, and low voltage detection circuit only. All peripheral functions other than the timebase timer, watch timer, and low voltage detection circuit stop. ● Stop mode The stop mode stops the oscillation clock (HCLK) and sub-clock (SCLK) during operation in each clock mode, and all functions other than low voltage detection circuit stop.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.2 Block Diagram of the Low-Power Consumption Control Circuit This section shows the block diagram of the low-power consumption control circuit. ■ Block Diagram of the Low-Power Consumption Control Circuit Figure 8.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ● CPU clock control circuit This circuit controls clocks supplied to the CPU. ● Pin high-impedance control circuit This circuit makes I/O pins high-impedance in the watch mode, timebase timer mode and stop mode. ● Internal reset generation circuit This circuit generates an internal reset signal. ● Low-power consumption mode control register (LPMCR) This register is used to switch to and release the standby mode and to set the CPU intermittent operation mode.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.3 Low-Power Consumption Mode Control Register (LPMCR) This register switches to or releases the low-power consumption mode. This register also generates the internal reset signal and sets the halt cycle count during the CPU intermittent operation mode. ■ Low-Power Consumption Mode Control Register (LPMCR) Figure 8.
CHAPTER 8 LOW-POWER CONSUMPTION MODE Table 8.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR) Bit name 140 Function bit7 STP: Stop mode bit This bit transits to the stop mode. When the bit is set to "0": No effect. When the bit is set to "1": The CPU enters the stop mode. Read: "0" is always read. • The bit is initialized to "0" when a reset or external interrupt occurs. bit6 SLP: Sleep mode bit This bit shift to sleep mode When the bit is set to "0": No effect.
CHAPTER 8 LOW-POWER CONSUMPTION MODE Notes: • Switching to a low-power consumption mode is performed by writing the low-power consumption mode control register (LPMCR). Only the instructions listed in Table 8.3-2 should be used for this purpose. If other instructions are used for switching to a low-power consumption mode, operation cannot be assured. • The standby mode transition instruction in Table 8.3-2 must always be followed by an array of instructions highlighted by a line below.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.4 CPU Intermittent Operation Mode This mode is used for intermittent operation of the CPU while operation clock is supplied to the CPU and peripheral functions. The purpose of this mode is to reduce power consumption. ■ CPU Intermittent Operation Mode This mode halts the supply of the clock pulse to the CPU for a certain period.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5 Standby Mode The standby mode causes the standby control circuit to either stop supplying an operation clock to the CPU or peripheral functions or to stop the oscillation clock reducing power consumption. ■ Operation Status during Standby Mode Table 8.5-1 shows operation status during standby mode. Table 8.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ❍: operation, ✕: stop, ◆: held in the state before transiting, Hi-Z: High impedance *1 : The timebase timer, watch timer, and low voltage detection function operate. *2 : The watch timer operates. *3 : The DTP/external interrupt input pin operates.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.1 Sleep Mode This mode causes the CPU operating clock to stop during operation in each clock mode. The CPU stops, and peripheral function operates. ■ Switching to Sleep Mode Writing 1 in the SLP bit and 0 in the STP bit of the low-power consumption mode control register (LPMCR) triggers a switch to a sleep mode according to setting of the MCS and SCS bits in the clock selection register (CKSCR). Table 8.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Operation during an interrupt request Writing 1 in the SLP bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt request, the CPU executes the next to currently executing instruction. If the CPU accepts the interrupt request, CPU operation immediately branches to the interrupt processing routine.
CHAPTER 8 LOW-POWER CONSUMPTION MODE Figure 8.5-1 Release of Sleep Mode by Interrupt Occurrence Set to interupt flag of resources INT generate (IL<7) YES NO No cancellation of sleep No cancellation of sleep Cancellation of sleep I=0 YES Execute the next instruction NO ILM
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.2 Watch Mode This mode causes all functions, excluding the subclock (SCLK), watch timer, and low voltage detection circuit, to stop. Main clock and PLL clock stop. ■ Switching to the Watch Mode When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the subclock run mode, switching to the watch mode occurs.
CHAPTER 8 LOW-POWER CONSUMPTION MODE identified according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR). In the sub-watch mode, no oscillation stabilization wait time is generated and the interrupt request is identified immediately after return from the watch mode. • When the CPU is not ready to accept any interrupt request, the next instruction to the currently executing instruction is executed.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.3 Timebase Timer Mode This mode causes all functions, excluding oscillation clock (HCLK), subclock (SCLK), the timebase timer, the watch timer, and low voltage detection circuit, to stop. In this mode, only the timebase timer, watch timer, and low voltage detection circuit, operate.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Return by interrupt When an interrupt request higher than interrupt level (IL) of 7 is generated from the watch timer, timebase timer, and external interrupt in the timebase timer mode, the timebase timer mode is cancelled.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.4 Stop Mode Because this mode causes oscillation clock (HCLK) and subclock (SCLK) to stop during operation in each clock mode, data can be retained by the lowest power consumption.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Status of pins Whether the I/O pins in the stop mode retain the state they had immediately before switching to the stop mode or go to the high-impedance state can be controlled by the SPL bit of the low-power consumption mode control register (LPMCR). Note: For those external pins shared between port functions and peripheral functions, disable output for the peripheral functions then set the STP bit to "1" to set these pins in high impedance state.
CHAPTER 8 LOW-POWER CONSUMPTION MODE ● Return by interrupt When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the stop mode, the stop mode is cancelled. In the stop mode, the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time is generated after the stop mode is cancelled.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.6 Status Change Diagram Figure 8.6-1 shows the operation status and status transition in the clock mode and standby mode of the MB90360 series. ■ Status Change Diagram Figure 8.6-1 Status Change Diagram Drop power supply voltage (4.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.7 Status of Pins in Standby Mode and during Hold and Reset The status of I/O pins in the standby mode and during hold and reset are described for each memory access mode. ■ Status of I/O Pins (Single-chip Mode) Table 8.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.8 Usage Notes on Low-Power Consumption Mode This section explains the notes when using the low-power consumption modes. ■ Transition to Standby Mode When an interrupt request is generated from the resource to the CPU, the mode does not transit to each standby mode even after setting the STP and SLP bits to 1 and the TMD bit to 0 in the low-power consumption mode control register (LPMCR) (and also even after interrupt processing).
CHAPTER 8 LOW-POWER CONSUMPTION MODE ● PLL clock oscillation stabilization wait time In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode till the PLL clock oscillation stabilization wait time has elapsed. When the main clock mode is switched to PLL clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation clock).
CHAPTER 8 LOW-POWER CONSUMPTION MODE The devices does not guarantee its operation after returning from the standby mode if you place an array of instructions other than the one enclosed in the line. ● To access the low-power consumption mode control register (LPMCR) with C language To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of the following methods 1. to 3. to access the register: 1.
CHAPTER 8 LOW-POWER CONSUMPTION MODE 160
CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. 9.
CHAPTER 9 MEMORY ACCESS MODES 9.1 Outline of Memory Access Modes In the F2MC-16LX, various modes are provided for access methods and access areas. ■ Outline of Memory Access Modes Table 9.1-1 Mode Pin and Mode Operation mode RUN mode Flash programming Bus mode Single-chip − ● Operation mode Operation mode means the mode for controlling the device operation status. The operation mode is specified by the MDx mode setting pin and the Mx bit in mode data.
CHAPTER 9 MEMORY ACCESS MODES 9.1.1 Mode Pins Table 9.1-2 lists the operations that can be specified by combining the three external pins MD2 to MD0. ■ Mode Pins Table 9.1-2 Mode Pin and Mode Mode pin setting MD2 MD1 MD0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode name Reset vector access area External data bus width Remarks Setting disabled Internal vector mode Internal (Mode data) Reset sequence and subsequent sequences are controlled by mode data.
CHAPTER 9 MEMORY ACCESS MODES 9.1.2 Mode Data Mode data is stored at FFFFDFH of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence. Always set the reserved bits to "0". ■ Mode Data Figure 9.
CHAPTER 9 MEMORY ACCESS MODES 9.1.3 Memory Space in Each Bus Mode Figure 9.1-2 shows the correspondence between the access areas and physical addresses for each bus mode. ■ Memory Space in Each Bus Mode Figure 9.
CHAPTER 9 MEMORY ACCESS MODES ■ Recommended Setting Table 9.1-4 lists an example of recommended settings for mode pins and mode data. Table 9.1-4 Recommended Setting Example of Mode Pin and Mode Data Setting example Single-chip MD2 MD1 MD0 0 1 1 External pins have signal functions that depend on each mode.
CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. 10.1 I/O Ports 10.
CHAPTER 10 I/O PORTS 10.1 I/O Ports Each pin of the ports can be specified as input or output using the port direction register (DDR) if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read. When a pin is specified as output, the port data register value is read. The above also applies to a read operation for the read-modify-write instructions.
CHAPTER 10 I/O PORTS 10.2 I/O Port Registers There are five types of I/O port registers: • Port data register (PDR2, PDR4 to PDR6, PDR8) • Port direction register (DDR2, DDR4 to DDR6, DDR8, DDRA) • Pull-up control register (PUCR2) • Analog input enable register (ADER5, ADER6) • Input level select register (ILSR0, ILSR1) ■ I/O Port Registers Figure 10.2-1 shows the I/O port registers. Figure 10.2-1 I/O Port Registers Bit No.
CHAPTER 10 I/O PORTS 10.2.1 Port Data Register (PDR) Note that R/W for I/O ports differ from R/W for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch. • Output mode Read: The port data register latch value is read. Write: Data is written to an output latch and outputted to the corresponding pin. Figure 10.2-2 shows the port data registers (PDR). ■ Port Data Register (PDR) Figure 10.
CHAPTER 10 I/O PORTS ● Reading the port data register The value obtained when reading the port data register (PDR) depends on the status of the port direction register (DDR) and status of the peripheral function connected to the pin. The following shows the value obtained by each combination.
CHAPTER 10 I/O PORTS 10.2.2 Port Direction Register (DDR) This register has following functions: • Setting the data direction of each pin that is used as a port. • Setting the input level of SIN -- Serial data input pin for LIN-UART. ■ Port Direction Register (DDR) Figure 10.2-3 shows the Port Direction Registers (DDR). Figure 10.2-3 Port Direction Registers (DDR) Bit No. DDR2 Address: 000012H Bit No. DDR4 Address: 000014H Bit No. DDR5 Address: 000015H Bit No. DDR6 Address: 000016H Bit No.
CHAPTER 10 I/O PORTS Table 10.2-1 SIN0/SIN1 Input Level Setting DDRA ILSR SIL0/SIL1 bit IL8 bit 0 0 Automotive level 0 1 CMOS level 1 x CMOS level SIN0(P82) / SIN1(P85) input level Note: SIL0, SIL1 are write-only, and “1” is always read from these bits. Therefore, instructions that perform a read-modify-write (RMW) operation such as the INC/DEC instruction, cannot be used at DDRA. ● DDRA: Bits 0 to 2, Bits 5 to 7 (unused bits) "1" is always read from these bits.
CHAPTER 10 I/O PORTS 10.2.3 Pull-up Control Register (PUCR) Each pin of port2 has programmable pull-up resistor. Each bit of this register controls corresponding pull-up resistor whether to be used or not. Figure 10.2-4 shows the pull-up control register (PUCR), and Figure 10.2-5 is the block diagram. ■ Pull-up Control Register (PUCR) Figure 10.2-4 Pull-up Control Register (PUCR) 7 Address: 00001EH 6 5 4 3 2 1 0 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 Read/Write Initial value Bit No.
CHAPTER 10 I/O PORTS 10.2.4 Analog Input Enable Register (ADER) Figure 10.2-6 shows the analog input enable register. ■ Analog Input Enable Registers (ADER) Figure 10.
CHAPTER 10 I/O PORTS 10.2.5 Input Level Select Register The input level select register allows to switch from Automotive Hysteresis input levels to CMOS Hysteresis input levels. ■ Input Level Select Register (ILSR) The input level select register ILSR is located on addresses 0EH and 0FH. Figure 10.
CHAPTER 10 I/O PORTS ■ Initial value of ILSR Initial value of each bit of ILSR is determined when external reset signal is released depending on the value of MD2, MD1, MD0 pin input, as shown in following table. About detail of each mode, please see "CHAPTER 9 MEMORY ACCESS MODES". Table 10.
CHAPTER 10 I/O PORTS 178
CHAPTER 11 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. 11.1 Overview of Timebase Timer 11.2 Block Diagram of Timebase Timer 11.3 Configuration of Timebase Timer 11.4 Interrupt of Timebase Timer 11.5 Explanation of Operations of Timebase Timer Functions 11.6 Precautions when Using Timebase Timer 11.
CHAPTER 11 TIMEBASE TIMER 11.1 Overview of Timebase Timer The timebase timer is an 18-bit free-run counter (timebase timer counter) that increments in synchronization with the main clock (half frequency of main oscillation clock). • Four interval times can be selected and an interrupt request can be generated for each interval time. • An operation clock is supplied to the oscillation stabilization wait time timer and other peripherals.
CHAPTER 11 TIMEBASE TIMER ■ Clock Supply The timebase timer supplies an operation clock to the resources such as an oscillation stabilization wait time timer, PPG timer, and watchdog timer. Table 11.1-2 shows the clock cycles supplied from the timebase timer to each resource. Table 11.1-2 Clock Cycles Supplied from Timebase Timer Where to supply clock Clock cycle Oscillation stabilization wait time* 210/HCLK (approx. 256 µs) 213/HCLK (approx. 2.0 ms) 215/HCLK (approx. 8.2 ms) 217/HCLK (approx. 32.
CHAPTER 11 TIMEBASE TIMER 11.2 Block Diagram of Timebase Timer The timebase timer consists of the following blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) ■ Block Diagram of Timebase Timer Figure 11.
CHAPTER 11 TIMEBASE TIMER ● Timebase timer counter The timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the oscillation clock (HCLK) as a count clock.
CHAPTER 11 TIMEBASE TIMER 11.3 Configuration of Timebase Timer This section explains the registers and interrupt factors of the timebase timer. ■ List of Registers and Reset Values of Timebase Timer Figure 11.
CHAPTER 11 TIMEBASE TIMER 11.3.1 Timebase timer control register (TBTC) The timebase timer control register (TBTC) provides the following settings: • Selecting the interval time of the timebase timer • Clearing the counter value of the timebase timer • Enabling or disabling the interrupt request when an overflow occurs • Checking and clearing the state of the interrupt request flag when an overflow occurs ■ Timebase Timer Control Register (TBTC) Figure 11.
CHAPTER 11 TIMEBASE TIMER Table 11.3-1 Functions of Timebase Timer Control Register (TBTC) Bit name Function bit15 Reserved: reserved bit Always set this bit to "1". bit14 bit13 Undefined bits Read: The value is undefined. Write: No effect bit12 TBIE: Overflow interrupt enable bit This bit enables or disables an interrupt when the interval timer bit in the timebase timer counter overflows. When set to "0": No interrupt request is generated at an overflow (TBOF = 1).
CHAPTER 11 TIMEBASE TIMER 11.4 Interrupt of Timebase Timer The timebase timer generates an interrupt request (interval timer function) when the interval time bit in the timebase timer counter corresponding to the interval time set by the timebase timer control register carries (overflows). ■ Interrupt of Timebase Timer • The timebase timer continues incrementing for as long as the main clock (with a half frequency of the oscillation clock) is inputted.
CHAPTER 11 TIMEBASE TIMER 11.5 Explanation of Operations of Timebase Timer Functions The timebase timer operates as an interval timer or an oscillation stabilization wait time timer. It also supplies a clock to peripherals. ■ Interval Timer Function Interrupt generation at every interval time enables the timebase timer to be used as an interval timer. Operating the timebase timer as an interval timer requires the settings shown in Figure 11.5-1 . ● Setting of timebase timer Figure 11.
CHAPTER 11 TIMEBASE TIMER At transition to the stop mode, the timebase timer counter is cleared to stop counting up. At return from the stop mode, the timebase timer counts the oscillation stabilization wait time of the main clock. Figure 11.
CHAPTER 11 TIMEBASE TIMER ■ Operation as Oscillation Stabilization Wait Time Timer The timebase timer can be used as the oscillation stabilization wait time timer for the main clock and PLL clock. The oscillation stabilization wait time is the time elapsed from when the timebase timer counter increments from "0" until the set oscillation stabilization wait time select bit overflows (carrying). Table 11.5-1 shows clearing conditions and oscillation stabilization wait time of timebase timer. Table 11.
CHAPTER 11 TIMEBASE TIMER Table 11.
CHAPTER 11 TIMEBASE TIMER 11.6 Precautions when Using Timebase Timer Precautions when using the timebase timer are shown below. ■ Precautions when Using Timebase Timer ● Clearing interrupt request To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF = 0), disable interrupts (TBTC: TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask register in the processor status.
CHAPTER 11 TIMEBASE TIMER 11.7 Program Example of Timebase Timer Programming examples for the timebase timer are shown below. ■ Program Example of Timebase Timer ● Processing specification The 212/HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly. In this case, the interval time is approximately 1.0 ms (at 4-MHz operation).
CHAPTER 11 TIMEBASE TIMER VECT 194 DSL ORG DSL DB ENDS END WARI 0FFDCH START 00H START ;Reset vector setting ;Setting to single-chip mode
CHAPTER 12 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. 12.1 Overview of Watchdog Timer 12.2 Configuration of Watchdog Timer 12.3 Watchdog Timer Registers 12.4 Explanation of Operations of Watchdog Timer Functions 12.5 Precautions when Using Watchdog Timer 12.
CHAPTER 12 WATCHDOG TIMER 12.1 Overview of Watchdog Timer The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a count clock. If the counter is not cleared within a set interval time, the CPU is reset. ■ Functions of Watchdog Timer • The watchdog timer is a timer counter that is used to prevent program malfunction. When the watchdog timer is started, the watchdog timer counter must continue to be cleared within a set interval time.
CHAPTER 12 WATCHDOG TIMER Table 12.1-1 Interval Time of Watchdog Timer Main Examples calculated Clock cycle External clock(@4MHz) CR oscillation Min. Max. Min. (@200kHz) (@50kHz) Max. 214 ± 211 /HCLK Approx. 3.58 ms Approx. 4.61 ms Approx. 0.072 s Approx. 0.369 s 216 ± 213 /HCLK Approx. 14.33 ms Approx. 18.4 ms Approx. 0.287 s Approx. 1.475 s 218 ± 215 /HCLK Approx. 57.34 ms Approx. 73.73 ms Approx. 1.147 s Approx. 5.898 s 221 ± 218 /HCLK Approx. 458.75 ms Approx. 589.
CHAPTER 12 WATCHDOG TIMER Notes: • When the timebase timer output (carry signal) is used as a count clock to the watchdog timer, clearing the timebase timer may extend the time for a watchdog reset to occur. • When the subclock is used as the machine cock, be sure to set the watchdog timer clock source select bit (WDCS) in the watch timer control register (WTC) to "0" to select the watch timer output.
CHAPTER 12 WATCHDOG TIMER 12.2 Configuration of Watchdog Timer The watchdog timer consists of the following blocks: • Count clock selector • Watchdog timer counter (2-bit counter) • Watchdog reset generator • Counter clear control circuit • Watchdog timer control register (WDTC) ■ Block Diagram of Watchdog Timer Figure 12.
CHAPTER 12 WATCHDOG TIMER ● Count clock selector The count clock selector selects a count clock input to the watchdog timer from the timebase timer or watch timer. Each timer output has four time intervals that can be set. ● Watchdog timer counter (2-bit counter) The watchdog timer counter is a 2-bit counter that uses the timebase timer output or watch timer output as a count clock. The clock source output destination is set by the watchdog clock select bit in the watch timer control register (WTC: WDCS).
CHAPTER 12 WATCHDOG TIMER 12.3 Watchdog Timer Registers This section explains the registers used for setting the watchdog timer. ■ List of Registers and Reset Values of Watchdog Timer Figure 12.
CHAPTER 12 WATCHDOG TIMER 12.3.1 Watchdog timer control register (WDTC) The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds reset factors. ■ Watchdog Timer Control Register (WDTC) Figure 12.
CHAPTER 12 WATCHDOG TIMER Table 12.3-1 Functions of the Watching Timer Control Register (WDTC) Bit name Function bit0 bit1 WT1, WT0: Interval time select bits These bits set the interval time of the watchdog timer.
CHAPTER 12 WATCHDOG TIMER 12.4 Explanation of Operations of Watchdog Timer Functions After starting, when the watchdog timer reaches the set interval time without the counter being cleared, a watchdog reset occurs. ■ Operations of Watchdog Timer The operation of the watchdog timer requires the settings shown in Figure 12.4-1 . Figure 12.
CHAPTER 12 WATCHDOG TIMER ● Clearing watchdog timer • When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within the interval time after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not cleared within the interval time, it overflows and the CPU is reset. • A reset, or transitions to the standby modes (sleep mode, stop mode, watch mode, timebase timer mode) clear the watchdog timer.
CHAPTER 12 WATCHDOG TIMER ● Checking reset factors The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can be read after a reset to check the reset factors. Reference: For details on the reset factor bit, see "CHAPTER 7 RESETS". Figure 12.
CHAPTER 12 WATCHDOG TIMER 12.5 Precautions when Using Watchdog Timer Take the following precautions when using the watchdog timer. ■ Precautions when Using Watchdog Timer ● Stopping watchdog timer The watchdog timer is stopped by all the reset sources. ● Interval time • The interval time uses the carry signal of the timebase timer or watch timer as a count clock. If the timebase timer or watch timer is cleared, the interval time of the watchdog timer may become long.
CHAPTER 12 WATCHDOG TIMER 12.6 Program Examples of Watchdog Timer Program example of watchdog timer is given below: ■ Program Examples of Watchdog Timer ● Processing specification • The watchdog timer is cleared each time in the loop of the main program. • The main program must be executed once within the minimum interval time of the watchdog timer.
CHAPTER 13 16-Bit I/O TIMER This chapter explains the function and operation of the 16- bit I/O timer. 13.1 Overview of 16-bit I/O Timer 13.2 Block Diagram of 16-bit I/O Timer 13.3 Configuration of 16-bit I/O Timer 13.4 Interrupts of 16-bit I/O Timer 13.5 Explanation of Operation of 16-bit Free-run Timer 13.6 Explanation of Operation of Input Capture 13.7 Precautions when Using 16-bit I/O Timer 13.
CHAPTER 13 16-Bit I/O TIMER 13.1 Overview of 16-bit I/O Timer The 16-bit I/O timer consists of one 16-bit free-run timer and 4 input capture. The timer can be performed the measurement of input pulse and external clock cycle based on the 16-bit free-run timer.
CHAPTER 13 16-Bit I/O TIMER 13.2 Block Diagram of 16-bit I/O Timer The 16-bit I/O timer consists of the following modules: • 16-bit free-run timer • Input capture ■ Block Diagram of 16-bit I/O Timer Figure 13.2-1 Block Diagram of 16-bit I/O Timer Internal data bus Input capture Dedicated bus 16-bit free-run timer ● 16-bit free-run timer The count value of the 16-bit free-run timer can be used as the base time for the input capture.
CHAPTER 13 16-Bit I/O TIMER ■ Details of Pins and Interrupt Number Table 13.2-1 shows the pins used by the 16-bit details of interrupt. Table 13.
CHAPTER 13 16-Bit I/O TIMER 13.2.1 Block Diagram of 16-bit Free-run Timer The MB90360 series contains 1 channel of the 16-bit free-run timer, and it consists of the following block. ■ Block Diagram of 16-bit Free-run Timer Figure 13.
CHAPTER 13 16-Bit I/O TIMER 13.2.2 Block Diagram of Input Capture The input capture consist of the following blocks: ■ Block Diagram of Input Capture Figure 13.
CHAPTER 13 16-Bit I/O TIMER ● Input capture data registers 0 to 3 (IPCP0 to IPCP3) • Input capture data register retains the counter value of the 16-bit free-run timer fetched by the capture operation.
CHAPTER 13 16-Bit I/O TIMER 13.3 Configuration of 16-bit I/O Timer This section explains the pins, registers, and interrupt factors of the 16-bit I/O timer. ■ Pins of 16-bit I/O Timer The pins of the 16-bit I/O timer serve as general-purpose I/O ports. Table 13.3-1 shows the pin functions and the pin settings required to use the 16-bit I/O timer. Table 13.
CHAPTER 13 16-Bit I/O TIMER 13.3.1 Timer Control Status Register (Upper) (TCCSH) Timer control status register (upper) selects the count clock and the conditions for clearing the counter, enables the count operation and interrupt, and checks the interrupt request flag. ■ Timer Control Status Register (Upper) (TCCSH) Figure 13.
CHAPTER 13 16-Bit I/O TIMER 13.3.2 Timer Control Status Register (Lower) (TCCSL) The timer control status register (Lower) selects the count clock and conditions for clearing the counter, clears the counter, enables the count operation or interrupt, and checks the interrupt request flag. ■ Timer Control Status Register (Lower) (TCCSL) Figure 13.
CHAPTER 13 16-Bit I/O TIMER Table 13.3-3 Functions of Timer Control Status Register (Lower) (TCCSL) Bit name Function bit7 IVF: Timer overflow generation flag bit This bit indicates the timer overflow. [Condition set to "1"] Condition is set when the following is used. • When 16-bit free-run timer overflows [When set to "1"] When the timer overflow interrupt request is set to enable (TCCSL:IVFE=1) if the IVF bit is set to "1", the interrupt request is generated. When set to "0": The bit is cleared.
CHAPTER 13 16-Bit I/O TIMER 13.3.3 Timer Data Register (TCDT) The timer data register is a 16-bit up counter. • The counter value of the 16-bit free-run timer is read. • The counter value can be set during stopping of the 16-bit free-run timer. ■ Timer Data Register (TCDT) Figure 13.
CHAPTER 13 16-Bit I/O TIMER 13.3.4 Input Capture Control Status Registers (ICS) The function of the input capture control status register is shown below. The correspondence between ICS01 to ICS23 and input pin is as follows. • ICS01: IN0, IN1 input capture ch0, ch1 • ICS23: IN2, IN3 input capture ch2, ch3 ■ Input Capture Control Status Registers (ICS01, ICS23) Figure 13.
CHAPTER 13 16-Bit I/O TIMER Table 13.3-4 Functions of Input Capture Control Status Register (ICS) Bit name Function bit7 ICPm: Valid edge detection flag bit m This bit is set to "1" when the valid edge is detected by the INm pin. When the interrupt request of the input capture m is set to enable (ICSnm:ICEm=1), if the ICPm bit is set, the interrupt request is generated. When set to "0": The bit is cleared. When set to "1": No effect.
CHAPTER 13 16-Bit I/O TIMER 13.3.5 Input Capture Register (IPCP) Input capture register stores the counter value fetched from 16-bit free-run timer by the capture operation. The IPCP register is the 16-bit read-only register and has the input capture registers 0 to 3 (IPCP0 to IPCP3). ■ Input Capture Register (IPCP) Figure 13.
CHAPTER 13 16-Bit I/O TIMER 13.3.6 Input Capture Edge Register (ICE) The input capture edge register has a function to indicate the selected edge direction and to select whether the input signal is inputted from either external pin or LIN-UART. By cooperating with the LIN-UART, the baud rate measurement at the LIN slave operation can be performed. The correspondence between ICE01 to ICE23 / channel name and input pin (UART) name is shown as follows.
CHAPTER 13 16-Bit I/O TIMER Table 13.3-5 Functions of Input Capture Edge Register 01 (ICE01) Bit name bit15 Function Undefined bits Read : The value is undefined. Write: No effect. bit12 ICUS1: Input signal selection bit 1 This bit selects the input signal used as the trigger of the input capture 1. When set to "0": Select the external pin IN1. When set to "1": Select the IN-UART1. bit11 Undefined bit Read : The value is undefined. Write: No effect.
CHAPTER 13 16-Bit I/O TIMER Table 13.3-6 Functions of Input Capture Edge Register 23 (ICE23) Bit name bit15 Function Undefined bits Read : The value is undefined. Write: No effect. bit9 IEI3: Detection edge indication bit 3 This bit indicates the edges detected by the input capture 3 (rising/falling). This bit is read only. "0": Indicate that falling edge is detected. "1": Indicate that rising edge is detected.
CHAPTER 13 16-Bit I/O TIMER 13.4 Interrupts of 16-bit I/O Timer The interrupt factors of the 16-bit I/O timer has overflow of the counter value in the 16bit free-run timer, trigger edge input to the input capture input pin, and trigger edge input for the LIN slave baud rate measurement from the LIN-UART. The EI2OS can be started by the interrupt of the input capture. ■ Interrupts of 16-bit I/O Timer Table 13.4-1 shows interrupt control bits and interrupt factors of 16-bit I/O timer. Table 13.
CHAPTER 13 16-Bit I/O TIMER ■ 16-bit I/O Timer Interrupt and EI2OS Reference: ■ For details of the interrupt number, interrupt control register, and interrupt vector address, see "CHAPTER 3 INTERRUPTS". Correspondence to EI2OS Function The input capture corresponds to the EI2OS function. However, to use the EI2OS function, it is necessary to disable other interrupt that shares the interrupt control register (ICR).
CHAPTER 13 16-Bit I/O TIMER 13.5 Explanation of Operation of 16-bit Free-run Timer After a reset, the 16-bit free-run timer starts incrementing from "0000H". The counter value of the 16-bit free-run timer is the base time of the input capture. ■ Explanation of Operation of 16-bit Free-run Timer Operation of the 16-bit free-run timer requires the setting shown in Figure 13.5-1 . Figure 13.
CHAPTER 13 16-Bit I/O TIMER Figure 13.5-2 shows counter clearing at an overflow. Figure 13.
CHAPTER 13 16-Bit I/O TIMER 13.6 Explanation of Operation of Input Capture The input capture stores the counter value of the 16-bit free-run timer to the input capture register at the timing that is detected the input signal of the valid edge from the external input pin or that the trigger edge for the LIN slave baud rate measurement is inputted, the interrupt request is generated. ■ Setting of Input Capture Operation of the input capture requires the setting shown in Figure 13.6-1 Figure 13.
CHAPTER 13 16-Bit I/O TIMER Figure 13.6-2 Timing of Fetching Data for Input Capture φ Counter value N N+1 Input capture input Valid edge Capture signal Capture register N+1 Data fetch φ: Machine clock Figure 13.6-3 Operation of Input Capture (Rising edge/falling edge) Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset INn (rising edge) INm (falling edge) Capture n Undefined Capture m Undefined 3FFFH 7FFFH n = 0, 2 m = n+1 Figure 13.
CHAPTER 13 16-Bit I/O TIMER 13.7 Precautions when Using 16-bit I/O Timer This section explains the precautions when using the 16-bit I/O timer. ■ Precautions when Using 16-bit I/O Timer ● Precautions when setting 16-bit free-run timer • Do not change the count clock select bits (TCCSL: CLK2, CLK1, CLK0) during the operation in the 16bit free-run timer (TCCSL: STOP = 0). • The counter value of the 16-bit free-run timer is cleared to "0000H" by reset.
CHAPTER 13 16-Bit I/O TIMER 13.8 Program Example of 16-bit I/O Timer This section gives a program example of the 16-bit I/O timer. ■ Program Example of 16-bit I/O Timer ● Processing specification • The cycle of a signal input to the IN0 pin is measured. • The 16-bit free-run timer 0 and input capture 0 are used. • The rising edge is selected as the trigger to be detected. • The machine clock (φ) is 24 MHz and the count clock of the free-run timer is 4/φ (0.17 µs).
CHAPTER 13 16-Bit I/O TIMER MOV MOV OR I:ICS01,#00010001B ;IN0 pin selection, External trigger, ;IPCP0 rising edge ;Without IPCP1 edge detection ;Clear each valid edge detection flag ;Input capture interrupt request enable ILM,#07H ;Set ILM in PS to level 7 CCR,#40H ;Interrupt enable LOOP: : User processing : BRA LOOP ;---------Interrupt program--------------------------------------------WARI0: CLRB I:ICP0 ;Clear valid edge detection flag : ;Save OV-CNT and input capture value User processing : MOV A,0
CHAPTER 13 16-Bit I/O TIMER 236
CHAPTER 14 16-BIT RELOAD TIMER This chapter describes the functions and operation of the 16-bit reload timer. 14.1 Overview of the 16-bit Reload Timer 14.2 Block Diagram of 16-bit Reload Timer 14.3 Configuration of 16-bit Reload Timer 14.4 Interrupts of 16-bit Reload Timer 14.5 Explanation of Operation of 16-bit Reload Timer 14.6 Precautions when Using 16-bit Reload Timer 14.
CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of the 16-bit Reload Timer The 16-bit reload timer has the following functions: • The count clock can be selected from three internal clocks and external event clocks. • A software trigger or external trigger can be selected as the start trigger. • If the 16-bit timer register (TMR) underflows, an interrupt can be generated to the CPU. The 16-bit reload timer can be used as an interval timer by using an interrupt.
CHAPTER 14 16-BIT RELOAD TIMER ■ Operation at Underflow When the start trigger is inputted, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16bit timer register, starting decrementing in synchronization with the count clock. When the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH", an underflow occurs. • When an underflow occurs with an underflow interrupt enabled (TMCSR:INTE = 1), an underflow interrupt is generated.
CHAPTER 14 16-BIT RELOAD TIMER 14.2 Block Diagram of 16-bit Reload Timer The 16-bit reload timers 2 and 3 composed of the following seven blocks: • Count clock generator • Reload controller • Output controller • Operation controller • 16-bit timer register (TMR) • 16-bit reload register (TMRLR) • Timer control status register (TMCSR) ■ Block Diagram of 16-bit Reload Timer Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER ● Details of pins in block diagram There are two channels for 16-bit reload timer. The actual pin names, outputs to resources, and interrupt request numbers for each channel are as follows: Table 14.
CHAPTER 14 16-BIT RELOAD TIMER 14.3 Configuration of 16-bit Reload Timer This section explains the pins, registers, and interrupt factors of the 16-bit reload timer. ■ Pins of 16-bit Reload Timer The pins of the 16-bit reload timer serve as general-purpose I/O ports. Table 14.3-1 shows the pin functions and the pin settings required to use the 16-bit reload timer. Table 14.
CHAPTER 14 16-BIT RELOAD TIMER ■ 16-bit Reload Timer Registers and Reset Value ● 16-bit reload timer 2 register Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER ■ Generation of Interrupt Request from 16-bit Reload Timer When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from "0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the UF bit in the timer control status register is set to 1 (TMCSR:UF). If an underflow interrupt is enabled (TMCSR:INTE = 1), an interrupt request is generated.
CHAPTER 14 16-BIT RELOAD TIMER 14.3.1 Timer Control Status Registers (High) (TMCSR:H) The timer control status registers (High) (TMCSR:H) set the operation mode and count clock. This section also explains the bit 7 in the timer control status registers (Low) (TMCSR:L). ■ Timer Control Status Registers (High) (TMCSR:H) Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER Table 14.3-2 Functions of Timer Control Status Registers (High) (TMCSR: H) Bit name 246 Function bit15 to bit12 Undefined bits Read: The value is undefined. Write: No effect bit11 bit10 CSL1, CSL0: Count clock select bits These bits select the count clock of the 16-bit reload timer. When set to anything other than "11B": These bit is counted by internal clock (internal clock mode). When set to "11B": The edge of the external event clock is counted (event count mode).
CHAPTER 14 16-BIT RELOAD TIMER 14.3.2 Timer Control Status Registers (Low) (TMCSR: L) The timer control status registers (Low) (TMCSR:L) enables or disable the timer operation, check the generation of a software trigger or an underflow, enables or disable an underflow interrupt, select the reload mode, and set the output of the TOT pin. ■ Timer Control Status Registers (Low) (TMCSR: L) Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER Table 14.3-3 Timer Control Status Registers (Low) (TMCSR: L) Bit Name 248 Function bit6 OUTE: TOT pin Output enable bit This bit sets the function of the TOT pin of the 16-bit reload timer. When set to 0: Functions as general-purpose I/O port When set to 1: Functions as TOT pin of 16-bit reload timer bit5 OUTL: TOT Pin output level select bit This bit sets the output level of the output pin of the 16-bit reload timer.
CHAPTER 14 16-BIT RELOAD TIMER 14.3.3 16-bit Timer Registers (TMR) The 16-bit timer registers are 16-bit down counters. At read, the value being counted is read. ■ 16-bit Timer Registers (TMR) Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER 14.3.4 16-bit Reload Registers (TMRLR) The 16-bit reload registers set the value to be reloaded to the 16-bit timer register (TMR). When the start trigger is inputted, the value set in the 16-bit reload registers is reloaded to the TMR, starting the TMR count operation. ■ 16-bit Reload Registers (TMRLR) Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER 14.4 Interrupts of 16-bit Reload Timer The 16-bit reload timer generates an interrupt request when the 16-bit timer register (TMR) underflows. ■ Interrupts of 16-bit Reload Timer When the value of the TMR is decremented from "0000H" to "FFFFH" during the TMR count operation, an underflow occurs. When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to l.
CHAPTER 14 16-BIT RELOAD TIMER 14.5 Explanation of Operation of 16-bit Reload Timer This section explains the setting of the 16-bit reload timer and the operation state of the counter. ■ Setting of 16-bit Reload Timer ● Setting of internal clock mode Counting the internal clock requires the setting shown in Figure 14.5-1 . Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER ■ Operating State of 16-bit Timer Register The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer control status register (TMCSR:CNTE) and the WAIT signal. The operating states include the stop state, start trigger input wait state (WAIT state), and RUN state. Figure 14.5-3 shows the state transition diagram for the 16-bit timer registers. Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER 14.5.1 Operation in Internal Clock Mode In the internal clock mode, three operation modes can be selected by setting the operating mode select bits in the timer control status register (TMCSR:MOD2 to MOD0).When the operation mode and reload mode are set, a rectangular wave or a toggle wave is outputted from the TOT pin.
CHAPTER 14 16-BIT RELOAD TIMER ■ Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to 1. • When the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) is set to 1, an underflow interrupt is generated.
CHAPTER 14 16-BIT RELOAD TIMER Figure 14.5-4 Count Operation in Software Trigger Mode (One-shot Mode) Counter clock Counter Reload data -1 0000H FFFFH Reload data -1 0000H FFFFH Data load signal UF bit CNTE bit TRG bit T* TOT pin Start trigger input wait T: Machine cycle * : It takes 1 machine cycle (time) to load data of reload register from trigger input. Figure 14.
CHAPTER 14 16-BIT RELOAD TIMER [External trigger mode (MOD2 to MOD0="001B", "010B", "011B")] When the external trigger mode is set, the 16-bit reload timer is started by inputting the external valid edge to the TIN pin. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count operation.
CHAPTER 14 16-BIT RELOAD TIMER [External gate input mode (MOD2 to MOD0="1x0B", "1x1B")] When the external gate input mode is set, start the 16-bit reload timer by setting the software trigger bit in the timer control status register (TMCSR:TRG) to 1. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR).
CHAPTER 14 16-BIT RELOAD TIMER 14.5.2 Operation in Event Count Mode In the event count mode, after the 16-bit reload timer is started, the edge of the signal input to the TIN pin is detected to perform the count operation of the 16-bit timer register (TMR). When the operation mode and the reload mode are set, a rectangular wave or a toggle wave is outputted from the TOT pin.
CHAPTER 14 16-BIT RELOAD TIMER ■ Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to 1. • When the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) is set to 1, an underflow interrupt is generated.
CHAPTER 14 16-BIT RELOAD TIMER ■ Operation in Event Count Mode The operation of the 16-bit reload timer is enabled by setting the timer operation enable bit in the timer control status register (TMCSR:CNTE) to 1. When the software trigger bit in the timer control status register (TMCSR:TRG) is set to 1, the 16-bit reload timer is started.
CHAPTER 14 16-BIT RELOAD TIMER 14.6 Precautions when Using 16-bit Reload Timer This section explains the precautions when using the 16-bit reload timer. ■ Precautions when Using 16-bit Reload Timer ● Precautions when setting by program • Set the 16-bit reload register (TMRLR) after disabling the timer operation (TMCSR:CNTE = 0) • The 16-bit timer register (TMR) can be read during the TMR count operation. However, always use the word instruction.
CHAPTER 14 16-BIT RELOAD TIMER 14.7 Sample Program of 16-bit Reload Timer This section gives a program example of the 16-bit reload timer operated in the internal clock mode and the event count mode: ■ Program Example in Internal Clock Mode ● Processing specification • The 24 ms interval timer interrupt is generated by the 16-bit reload timer 2. • The repeated interrupts are generated in the reload mode. • The timer is started using the software trigger instead of the external trigger input.
CHAPTER 14 16-BIT RELOAD TIMER BRA LOOP ; ;---------Interrupt program----------------------------------WARI: CLR I:UF2 ;Interrupt request flag cleared : : Processing by user : : RETI ;Return from interrupt CODE ENDS ;---------Vector setting---------------------------------------VECT CSEG ABS=0FFH ORG 00FFB0H ;Set vector to interrupt #19(13H) VECT DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H ;Reset vector set ;Set to single-chip mode START ■ Program Example in Event Counter Mode ● Processing specifi
CHAPTER 14 16-BIT RELOAD TIMER AND MOV MOV CLRB MOVW MOVW MOV OR CCR,#0BFH ;Interrupts disabled I:ICR04,#00H ;Interrupt level 0 (highest) I:DDR8,00H ;Sets P82/TIN2 pin to input I:CNTE0 ;Counter suspended I:TMRLR2,#2710H;Reload value set to 10000 times I:TMCSR2,#0000110001001011B ;Counter operation, rising edge, ;and external output disabled ;One-shot mode selected, interrupt enabled ;Interrupt flag cleared, count started ILM,#07H ;Set ILM in PS to level 7 CCR,#40H ;Interrupts enabled LOOP: : Processing
CHAPTER 14 16-BIT RELOAD TIMER 266
CHAPTER 15 WATCH TIMER This chapter describes the functions and operations of the watch timer. 15.1 Overview of Watch Timer 15.2 Block Diagram of Watch Timer 15.3 Configuration of Watch Timer 15.4 Watch Timer Interrupt 15.5 Explanation of Operation of Watch Timer 15.
CHAPTER 15 WATCH TIMER 15.1 Overview of Watch Timer The watch timer is a 15-bit free-run counter that increments in synchronization with the subclock. • Eight interval times can be selected and an interrupt request can be generated for each interval time. • An operation clock can be supplied to the oscillation stabilization wait time timer of the subclock and the watchdog timer. • The subclock is always used as a count clock regardless of the settings of the clock select register (CKSCR).
CHAPTER 15 WATCH TIMER ■ Cycle of Clock Supply The watch timer supplies an operation clock to the oscillation stabilization wait time timer of the subclock and the watchdog timer. Table 15.1-2 shows the cycles of clocks supplied from the watch timer. Table 15.1-2 Cycle of Clock Supplied from Watch Timer Where to Supply Clock Timer for oscillation stabilization wait time of subclock Clock Cycle 214/SCLK(4.000 s) 210/SCLK(125 ms) 213/SCLK(1.000 s) Watchdog timer 214/SCLK(2.000 s) 215/SCLK(4.
CHAPTER 15 WATCH TIMER 15.2 Block Diagram of Watch Timer The watch timer consists of the following blocks: • Watch timer counter • Counter clear circuit • Interval timer selector • Watch timer control register (WTC) ■ Block Diagram of Watch Timer Figure 15.
CHAPTER 15 WATCH TIMER ● Interval timer selector The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time set in the watch timer control register (WTC). ● Watch timer control register (WTC) The watch timer control register (WTC) selects the interval time, clears the watch timer counter, enables or disables an interrupt, checks the overflow (carry) state, and clears the overflow flag bit.
CHAPTER 15 WATCH TIMER 15.3 Configuration of Watch Timer This section explains the registers and interrupt factors of the watch timer. ■ List of Registers and Reset Values of Watch Timer Figure 15.
CHAPTER 15 WATCH TIMER 15.3.1 Watch Timer Control Register (WTC) This section explains the functions of the watch timer control register (WTC). ■ Watch Timer Control Register (WTC) Figure 15.3-2 Watch Timer Control Register (WTC) Address 0000AAH 7 6 5 4 3 2 1 0 Reset value WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 R/W R 1X001000 B R/W R/W R/W R/W R/W R/W bit2 bit1 bit0 WTC2 WTC1 WTC0 Interval time select bit 0 0 0 28/SCLK(31.25 ms) 0 0 1 29/SCLK(62.
CHAPTER 15 WATCH TIMER Table 15.3-1 Functions of Watch Timer Control Register (WTC) Bit Name Function bit7 WDCS: Watchdog clock select bit This bit selects the operation clock of the watchdog timer. When set to "0": Selects output of watch timer as operation clock of watchdog timer. When set to "1": Selects output of timebase timer as operation clock of watchdog timer. Always set this bit to 0 to select the output of the watch timer.
CHAPTER 15 WATCH TIMER 15.4 Watch Timer Interrupt When the interval time is reached with the watch timer interrupt enabled, the overflow flag bit is set to "1" and an interrupt request is generated. ■ Watch Timer Interrupt Table 15.4-1 shows the interrupt control bits and interrupt factors of the watch timer. Table 15.
CHAPTER 15 WATCH TIMER 15.5 Explanation of Operation of Watch Timer The watch timer operates as an interval timer or an oscillation stabilization wait time timer of subclock. It also supplies an operation clock to the watchdog timer. ■ Watch Timer Counter The watch timer counter continues incrementing in synchronization with the subclock (SCLK) while the subclock (SCLK) is operating. ● Clearing watch timer counter The watch timer counter is cleared to "0000H" when: • A power-on reset occurs.
CHAPTER 15 WATCH TIMER ● Clearing overflow flag bit (WTC:WTOF) When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait time timer of subclock. The WTOF bit is cleared concurrently with mode switching. ■ Setting Operation Clock of Watchdog Timer The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the clock input source of the watchdog timer.
CHAPTER 15 WATCH TIMER 15.6 Program Example of Watch Timer This section gives a program example of the watch timer. ■ Program Example of Watch Timer ● Processing specifications An interval interrupt at 213/SCLK (SCLK: subclock) is generated repeatedly. The internal time is approximately 1.0 s (when subclock operates at 8.192 kHz).
CHAPTER 15 WATCH TIMER VECT ORG DSL DB ENDS END 00FFDCH START 00H ;Reset vector set ;Set to single-chip mode START 279
CHAPTER 15 WATCH TIMER 280
CHAPTER 16 8-/16-BIT PPG TIMER This chapter describes the functions and operations of the 8-/16-bit PPG timer. 16.1 Overview of 8-/16-bit PPG Timer 16.2 Block Diagram of 8-/16-bit PPG Timer 16.3 Configuration of 8-/16-bit PPG Timer 16.4 Interrupts of 8-/16-bit PPG Timer 16.5 Explanation of Operation of 8-/16-bit PPG Timer 16.
CHAPTER 16 8-/16-BIT PPG TIMER 16.1 Overview of 8-/16-bit PPG Timer The 8-/16-bit PPG timer is a reload timer module with two channels (PPGC and PPGD) that outputs a pulse in any cycle and at any duty ratio. A combination of two channels provides: • 8-bit PPG output 2-channel independent operation mode • 16-bit PPG output operation mode • 8+8-bit PPG output operation mode The MB90360 series has two 8-/16-bit PPG timers. This section explains the functions of PPGC/D.
CHAPTER 16 8-/16-BIT PPG TIMER ■ Operation Modes of 8-/16-bit PPG Timer ● 8-bit PPG output 2-channel independent operation mode The 8-bit PPG output 2-channel independent operation mode causes the 2-channel modules (PPGC and PPGD) to operate as each independent 8-bit PPG timer. Table 16.1-1 shows the interval times in the 8-bit PPG output 2-channel independent operation mode. Table 16.
CHAPTER 16 8-/16-BIT PPG TIMER ● 8+8-bit PPG output operation mode The 8 + 8-bit PPG output operation mode causes the PPGC of the 2-channel modules to operate as an 8-bit prescaler and the underflow output of the PPGC to operate as the count clock of the PPGD. Table 16.1-3 shows the interval times in this mode. Table 16.1-3 Interval Times in 8+8-bit PPG Output Operation Mode PPGC PPGD Count Clock Cycle Interval Time Output Pulse Time Interval Time Output Pulse Time 1/φ(41.
CHAPTER 16 8-/16-BIT PPG TIMER 16.2 Block Diagram of 8-/16-bit PPG Timer The MB90360 series contains two 8-/16-bit PPG timers (each with 2 channels). One 8-/16-bit PPG timer consists of 8-bit PPG timers with two channels. This section shows the block diagrams for the 8-/16-bit PPG timer C and 8-/16-bit PPG timer D. The PPGE has the same function as the PPGC, and PPGF has the same function as PPGD. ■ Channels and PPG Pins of PPG Timers Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER 16.2.1 Block Diagram for 8-/16-bit PPG Timer C The 8-/16-bit PPG timer C consists of the following blocks. ■ Block Diagram of 8-/16-bit PPG Timer C Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER ● Details of pins in block diagram Table 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 16.
CHAPTER 16 8-/16-BIT PPG TIMER 16.2.2 Block Diagram of 8-/16-bit PPG Timer D The 8-/16-bit PPG timer D consists of the following blocks. ■ Block Diagram of 8-/16-bit PPG Timer D Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER ● Details of pins in block diagram Table 16.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 16.
CHAPTER 16 8-/16-BIT PPG TIMER 16.3 Configuration of 8-/16-bit PPG Timer This section explains the pins, registers and interrupt factors of the 8-/16-bit PPG timer. ■ Pins of 8-/16-bit PPG Timer The pins of the 8-/16-bit PPG timer serve as general-purpose I/O ports. Table 16.3-1 indicates the pin functions and pin settings required to use the 8-/16-bit PPG timer. Table 16.
CHAPTER 16 8-/16-BIT PPG TIMER ■ List of Registers and Reset Values of 8-/16-bit PPG Timer Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.1 PPGC Operation Mode Control Register (PPGCC) The PPGC operation mode control register (PPGC0) provides the following settings for the operation of 8-/16-bit PPG timer C: • Enabling or disabling operation of 8-/16-bit PPG timer C • Switching between pin functions (enabling or disabling pulse output) • Enabling or disabling underflow interrupt • Setting underflow interrupt request flag This section explains the PPGCC function only.
CHAPTER 16 8-/16-BIT PPG TIMER Table 16.3-2 Functions of PPGC Operation Mode Control Register (PPGCC) Bit Name Function bit7 PEN0: PPG0 operation enable bit This bit enables or disables the count operation of the 8-/16-bit PPG timer C. When set to "0": Count operation disabled When set to "1": Count operation enabled • When the count operation is disabled (PEN0=0), and the pulse output is enabled (PE0=1), the output is held at a Low level. bit6 Undefined bit Read: The value is undefined.
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.
CHAPTER 16 8-/16-BIT PPG TIMER Table 16.3-3 Functions of PPGD Operation Mode Control Register (PPGCD) Bit name Function bit15 PEN1: PPG1 operation enable bit This bit enables or disables the count operation of the 8-/16-bit PPG timer D. When set to "0": Count operation disabled When set to "1": Count operation enabled • When the count operation is disabled (PEN1 = 0), and the pulse output is enabled (PE1=1), the output is held at a Low level. bit14 Undefined bit Read: The value is undefined.
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.3 PPGC/D Count Clock Select Register (PPGCD) The PPGC/D count clock select register selects the count clock of the 8-/16-bit PPG timers C and D and the output pin. This section explains the PPGCD function only. The PPGEF has the same function as the PPGCD, and the 8-/16-bit PPG timers E and F are set. ■ PPGC/D Count Clock Select Register (PPGCD) Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER Table 16.3-4 Functions of PPGC/D Count Clock Select Register (PPGCD) Bit Name Function bit7 to bit5 PCS2 to PCS0: PPGD count clock select bits These bits set the count clock of the 8-/16-bit PPG timer D. • The count clock can be selected from five frequency-divided clocks of the machine clock and the frequency-divided clocks of the timebase timer.
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.4 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD) The value (reload value) from which the PPG down counter starts counting is set in the PPG reload registers, which are an 8-bit register at Low level and an 8-bit register at High level. This section explains the function of PRLLC/PRLHC and PRLLD/PRLHD only. The PRLLE/PRLHE, PRLLF/PRLHF have the same function as the PRLLC/PRLHC, and the 8-/ 16-bit PPG timers E, F are set.
CHAPTER 16 8-/16-BIT PPG TIMER 16.4 Interrupts of 8-/16-bit PPG Timer The 8-/16-bit PPG timer can generate an interrupt request when the PPG down counter underflows. It also not corresponds to the EI2OS. ■ Interrupts of 8-/16-bit PPG Timer Table 16.4-1 shows the interrupt control bits and interrupt factor of the 8-/16-bit PPG timer. Table 16.
CHAPTER 16 8-/16-BIT PPG TIMER 16.5 Explanation of Operation of 8-/16-bit PPG Timer The 8-/16-bit PPG timer outputs a pulse width at any frequency and at any duty ratio continuously. ■ Operation of 8-/16-bit PPG Timer ● Output operation of 8-/16-bit PPG timer • The 8-/16-bit PPG timer has two (Low-level and High-level) 8-bit reload registers (PRLLn/PRLHn and PRLLm/PRLHm) for per channel.
CHAPTER 16 8-/16-BIT PPG TIMER 16.5.1 8-bit PPG Output 2-channel Independent Operation Mode In the 8-bit PPG output 2-channel independent operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG timer with two independent channels. PPG output operation and interrupt request generation can be performed independently for each channel.
CHAPTER 16 8-/16-BIT PPG TIMER ● Operation in 8-bit PPG output 2-channel independent operation mode • The 8-bit PPG timer with two channels performs an independent PPG operation. • When the pin output is enabled (PPGCn: PEC=1, PPGCm: PED=1), if the PPG output pin selection is set to standard (PPGnm:REV=0), the PPGn pulse wave is outputted from the PPGn pin and the PPGm pulse wave is outputted from the PPGm pin.
CHAPTER 16 8-/16-BIT PPG TIMER ● Output waveform in 8-bit PPG output 2-channel independent operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is "00H", the pulse width has one count clock cycle, and if the value is "FFH", the pulse width has 256 count clock cycles.
CHAPTER 16 8-/16-BIT PPG TIMER 16.5.2 16-bit PPG Output Operation Mode In the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a 16-bit PPG timer with one channel. ■ Setting for 16-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 16-bit PPG output operation mode requires the setting shown in Figure 16.5-4 . Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER ● Operation in 16-bit PPG output operation mode • When either PPGn pin output or PPGm pin output is enabled (PPGCn:PEC=1, PPGCm: PED=1), the same pulse wave is outputted from both the PPGn and PPGm pins. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable operation of the PPG timer (PPGCn:PENC=1 and PPGCm: PEND=1), the PPG down counters start counting as 16-bit down counters (PCNTn + PCNTm).
CHAPTER 16 8-/16-BIT PPG TIMER ● Output waveform in 16-bit PPG output operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is "0000H", the pulse width has one count clock cycle, and if the value is "FFFFH", the pulse width has 65,536 count clock cycles.
CHAPTER 16 8-/16-BIT PPG TIMER 16.5.3 8+8-bit PPG Output Operation Mode In the 8 + 8-bit PPG output operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG timer. The PPGC operates as an 8-bit prescaler and the PPG operates using the PPG output of the PPGC as a clock source. ■ Setting for 8+8-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in Figure 16.5-6 . Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER ● Operation in 8+8-bit PPG output operation mode • The PPGn operates as the prescaler of the PPGm timer and the PPGm operates using the PPGn output as a clock source. • When the pin output is enabled (PPGCn: PE0=1, PPGCm: PE1=1) if PPG output pin selection is set to standard (PPGnm:REV=0), PPGn pulse wave is outputted from the PPGn pin and the PPGm pulse wave is outputted from the PPGm pin.
CHAPTER 16 8-/16-BIT PPG TIMER ● Output waveform in 8+8-bit PPG output operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle.
CHAPTER 16 8-/16-BIT PPG TIMER 16.6 Precautions when Using 8-/16-bit PPG Timer This section explains the precautions when using the 8-/16-bit PPG timer.
CHAPTER 16 8-/16-BIT PPG TIMER Figure 16.
CHAPTER 16 8-/16-BIT PPG TIMER Figure 16.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS This chapter explains the functions and operations of DTP/external interrupt. 17.1 Overview of DTP/External Interrupt 17.2 Block Diagram of DTP/External Interrupt 17.3 Configuration of DTP/External Interrupt 17.4 Explanation of Operation of DTP/External Interrupt 17.5 Precautions when Using DTP/External Interrupt 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.1 Overview of DTP/External Interrupt The DTP/external interrupt sends interrupt requests from external peripheral devices or data transfer requests to the CPU to generate an external interrupt request, or starts the EI2OS. ■ DTP/External Interrupt Function The DTP/external interrupt follows the same procedure as resource interrupts to send interrupt requests from external peripheral devices to the CPU to generate an external interrupt request, or starts the EI2OS.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.2 Block Diagram of DTP/External Interrupt The block diagram of the DTP/external interrupt is shown below. ■ Block Diagram of DTP/External Interrupt Figure 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ● DTP/external interrupt input detection circuit This circuit detects interrupt requests or data transfer requests generated from external peripheral devices. The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting register (ELVR) is detected is set to "1" (EIRR1:ER).
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3 Configuration of DTP/External Interrupt This section lists and details the pins, interrupt factors, and registers in the DTP/ external interrupt. ■ Pins of DTP/External Interrupt The pins used by the DTP/external interrupt serve as general-purpose I/O ports. Table 17.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt. Table 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ■ List of Registers and Reset Values in DTP/External Interrupt Figure 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.1 DTP/External Interrupt Factor Register (EIRR1) The DTP/external interrupt factor register holds DTP/external interrupt factors. When a valid signal is inputted to the DTP/external interrupt pin, the corresponding DTP/external interrupt request flag bit is set to "1". The EIRR1 register is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R, and INT15R. ■ DTP/External Interrupt Factor Register (EIRR1) Figure 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-2 Function of DTP/External Interrupt Factor Register (EIRR1) Bit Name bit8 to bit15 320 ER15 to ER8(EIRR1), DTP/External interrupt request flag bits Function These bits are set to "1" when the edges or level signals set by the detection condition select bits in the detection level setting register (ELVR1:LB, LA) are inputted to the DTP/external interrupt pins.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.2 DTP/External Interrupt Enable Register (ENIR1) The DTP/external interrupt enable register (ENIR1) enables/disables the DTP/external interrupt request in the external peripheral devices. ENIR1 is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R and INT15R. ■ DTP/External Interrupt Enable Register (ENIR1) Figure 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.3 Detection Level Setting Register (ELVR1) The detection level setting register sets the level or edge of input signals that cause the interrupt factors of the DTP/external interrupt pin. ELVR1 is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R and INT15R. ■ Detection Level Setting Register (ELVR1) Figure 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.3.4 External Interrupt Factor Select Register (EISSR) The external interrupt factor select register (EISSR) can change the assignment of the external interrupt pin. This allows the external interrupt. Also, the function such as CAN wakeup is implemented. ■ Selection of External Interrupt Factor The external interrupt pin of the upper 8-bit is assigned to INT13, INT11, INT10, and INT8 normally and shares the port 5 and pin.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4 Explanation of Operation of DTP/External Interrupt The DTP/external interrupt has an external interrupt function and a DTP function. The setting and operation of each function are explained. ■ Setting of DTP/External Interrupt Using the DTP/external interrupt requires, the setting shown in Figure 17.4-1 . Figure 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ● Setting procedure To use the DTP/external interrupt, set each register by using the following procedure: 1. Set the input port to the general-purpose I/O port, which is shared with the terminal to be used as external interrupt input. 2. Set the external interrupt factor select register (EISSR) corresponding to the DTP/external interrupt channel to be used. 3.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ■ DTP/External Interrupt Operation The control bits and the interrupt factors for the DTP/external interrupt are shown in Table 17.4-1 . Table 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS Figure 17.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4.1 External Interrupt Function The DTP/external interrupt has an external interrupt function for generating an interrupt request by detecting the signal (edge or level) in the DTP/external interrupt pin. ■ External Interrupt Function • When the signal (edge or level) set in the detection level setting register is detected in the DTP/external interrupt pin, the interrupt request flag bit in the DTP/external interrupt factor register (EIRR1:ER) is set to "1".
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4.2 DTP Function The DTP/external interrupt has the DTP function that detects the signal of the external peripheral device from the DTP/external interrupt pin to start the EI2OS. ■ DTP Function The DTP function detects the signal level set by the detection level setting register of the DTP/external interrupt function to start the EI2OS.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.5 Precautions when Using DTP/External Interrupt This section explains the precautions when using the DTP/external interrupt. ■ Precautions when Using DTP/External Interrupt ● Condition of external-connected peripheral device when DTP function is used • When using the DTP function, the peripheral device must automatically clear a data transfer request when data transfer is performed.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ● Precautions on interrupts • When the DTP/external interrupt is used as the external interrupt function, no return from interrupt processing can be made with the DTP/external interrupt request flag bit set to "1" (EIRR1:ER) and the DTP/external interrupt request set to "enabled" (ENIR1:EN = 1). Always set the DTP/external interrupt request flag bit to 0 (EIRR1:ER) at interrupt processing.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.6 Program Example of DTP/External Interrupt Function This section gives a program example of the DTP/external interrupt function. ■ Program Example of DTP/External Interrupt Function ● Processing specifications An external interrupt is generated by detecting the rising edge of the pulse input to the INT8 pin.
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ÅE Processing by user ÅE RETI ;Return from interrupt processing CODE ENDS ;---------Vector setting-----------------------------------------VECT CSEG ABS=0FFH ORG 00FF94H ;Set vector to interrupt number #26(1AH) VECT DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H ;Reset vector set ;Set to single-chip mode START ■ Program Example of DTP Function ● Processing specification • Channel 0 of the EI2OS is started by detecting the High level of the signal input to the INT8 p
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ; ;---------Main program------------------------------------CODE CSEG START: ;Stack pointer (SP) already initialized MOV I:ADER5,#00000000B ;Set analog input of port5 to disable MOV I:ADER6,#00000000B ;Set analog input of port6 to disable MOV I:DDR6,#11111111B ;Set DDR6 to output port MOV I:DDR5,#00000000B ;Set DDR5 to input port AND CCR,#0BFH ;Interrupts disabled MOV I:ICR07,#08H ;Interrupt level 0 (highest) EI2OS ;Channel 0 ;Data bank register (DTB) = 00H MOV BAPL,#0
CHAPTER 17 DTP/EXTERNAL INTERRUPTS #26(1AH) VECT 338 DSL ORG DSL DB ENDS END WARI 00FFDCH START 00H START ;Reset vector set ;Set to single-chip mode
CHAPTER 18 8-/10-BIT A/D CONVERTER This chapter explains the functions and operation of 8-/ 10-bit A/D converter. 18.1 Overview of 8-/10-bit A/D Converter 18.2 Block Diagram of 8-/10-bit A/D Converter 18.3 Configuration of 8-/10-bit A/D Converter 18.4 Interrupt of 8-/10-bit A/D Converter 18.5 Explanation of Operation of 8-/10-bit A/D Converter 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.1 Overview of 8-/10-bit A/D Converter The 8-/10-bit A/D converter converts the analog input voltage to a 8- or 10-bit digital value by using the RC sequential-comparison converter system. • An input signal can be selected from the input signals of the analog input pins for 16 channels. • The start trigger can be selected from a software trigger and an external trigger.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.2 Block Diagram of 8-/10-bit A/D Converter The 8-/10-bit A/D converter consists of following blocks. ■ Block Diagram of 8-/10-bit A/D Converter Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER ● Details of pins in block diagram Table 18.2-1 shows the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter. Table 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER ● Analog channel selector This selector selects the pin to be used for A/D conversion from the 16-channel analog input pins by receiving a signal from the decoder. ● Sample & hold circuit This circuit holds the input voltage selected by the analog channel selector. By holding the input voltage immediately after A/D conversion is started, A/D conversion is performed without being affected by the fluctuation of the input voltage during A/D conversion.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3 Configuration of 8-/10-bit A/D Converter This section explains the pins, registers, and interrupt factors of the A/D converter. ■ Pins of 8-/10-bit A/D Converter The pins of the 8-/10-bit A/D converter serve as general-purpose I/O ports. Table 18.3-1 shows the pin functions and the setting required for use of the 8-/10-bit A/D converter. Table 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER ■ List of Registers and Reset Values of 8-/10-bit A/D Converter Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.
CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS1) (1/2) Bit name Function bit15 BUSY: A/D conversion-on flag bit This bit forcibly terminates the 8-/10-bit A/D converter. When read, this bit indicates whether the 8-/10-bit A/D converter is operating or stopped.
CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS1) (2/2) Bit name 348 Function bit12 PAUS: Pause flag bit This bit indicates the A/D conversion operating state when the EI2OS function is used. • The PAUS bit is enabled only when the EI2OS function is used.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.2 A/D Control Status Register (Low) (ADCS0) The A/D control status register (Low) (ADCS0) provides the following settings: • Selecting A/D conversion mode • Selecting start channel and end channel of A/D conversion ■ A/D Control Status Register (Low) (ADCS0) Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS0) Bit Name Function bit7 bit6 MD1, MD0: A/D conversion mode select bits These bits set the A/D conversion mode. Single-shot conversion mode 1: • The analog inputs from the start channel (ADSR0 : ANS3 to ANS0) to the end channel (ADSR0 : ANE3 to ANE0) are A/D-converted continuously. • The A/D conversion pauses after A/D conversion for the end channel.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.3 A/D Data Register (ADCR0/ADCR1) The A/D data register (ADCR0/ADCR1) stores the digital value generated as the conversion result. The ADCR0 stores the lower 8-bit, and ADCR1 stores the most significant 2-bit of the conversion result. This register is rewritten each time the conversion complete and stores last conversion value normally. ■ A/D Data Register (ADCR0/ADCR1) Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.4 A/D Setting Register (ADSR0/ADSR1) A/D setting register (ADSR0/ADSR1) can set as following. • Setting of A/D conversion time (sampling time and comparing time) • Setting of sampling channel (starting channel and end channel) • Displaying the present sampling channels ■ A/D Setting Register (ADSR0/ADSR1) Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (1/2) Bit Name Function bit15 to bit13 ST2, ST1, ST0: Sampling time select bits These bits set the sampling time of A/D conversion. • These bits set the time when the A/D conversion is started and inputted analog voltage is sampled by the sample & hold circuit until it is retained. • See Table 18.3-6 for the setting of these bits.
CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (2/2) Bit Name bit3 to bit0 Function ANE3 to ANE0: A/D conversion end channel select bits These bits set the channel at which A/D conversion terminated.
CHAPTER 18 8-/10-BIT A/D CONVERTER The sampling time must be set according to drive impedance Rext connected to analog input. If the following condition is not met, the conversion accuracy will not be guaranteed. • Rext ≤ 1.5kΩ : •- 4.5 V ≤ AVCC < 5.5 V: The sampling time must be set greater than 0.5 µs. • 4.0 V ≤ AVCC < 4.5 V: The sampling time must be set greater than 1.2 µs. • Rext > 1.5kΩ : The sampling time must be set greater than Tsamp given by the following formula. • 4.5 V ≤ AVCC < 5.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.5 Analog Input Enable Register (ADER5, ADER6) The analog input enable register enables or disables the analog input pins to be used in the 8-/10-bit A/D converter. ■ Analog Input Enable Register (ADER5, ADER 6) Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER Notes: • When using as the analog input pin, write "1" to the bit of the analog input enable register (ADER5, ADER6) corresponding to the pin to be used and set to the analog input. • Setting the analog input pin to ADERx = "0" is disabled. Always set it to ADERx = "1". • Each analog input pin serves as the general-purpose I/O port and I/O of peripheral function.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.4 Interrupt of 8-/10-bit A/D Converter When A/D conversion is terminated and its results are stored in the A/D data register (ADCR), the 8-/10-bit A/D converter generates an interrupt request. The EI2OS function can be used. ■ Interrupt of A/D Converter When A/D conversion of the analog input voltage is terminated and its results are stored in the A/D data register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS:INT) is set to "1".
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5 Explanation of Operation of 8-/10-bit A/D Converter The 8-/10-bit A/D converter has the following A/D conversion modes. Set each mode according to the setting of the A/D conversion mode select bits in the A/D control status register (ADCS:MD1, MD0).
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.1 Single-shot Conversion Mode In the single-shot conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. The A/D conversion stops at the termination of A/D conversion for the end channel. ■ Setting of Single-shot Conversion Mode Operating the 8-/10-bit A/D converter in the single-shot conversion mode requires the setting shown in Figure 18.5-1 . Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER ■ Operation of Single-shot Conversion Mode • When the start trigger is inputted, A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS3 to ANS0) and is performed continuously up to the channel set by the A/ D conversion end channel select bits (ANE3 to ANE0). • The A/D conversion stops at the termination of the A/D conversion for the channel set by the A/D conversion end channel select bits (ANE3 to ANE0).
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.2 Continuous Conversion Mode In the continuous conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. When A/D conversion for the end channel is terminated, it is continued after returning to the start channel. ■ Setting of Continuous Conversion Mode Operating the 8-/10-bit A/D converter in the continuous conversion mode requires the setting shown in Figure 18.5-2 . Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER ■ Operation of Continuous Conversion Mode • When the start trigger is inputted, A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS3 to ANS0) and is performed continuously up to the channel set by the A/ D conversion end channel select bits (ANE3 to ANE0).
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.3 Pause-conversion Mode In the pause-conversion mode, A/D conversion starts and pauses repeatedly for each channel. When the start trigger is inputted after the A/D conversion pauses at the termination of the A/D conversion for the end channel, A/D conversion is continued after returning to the start channel. ■ Setting of Pause-conversion Mode Operating the 8-/10-bit A/D converter in the pause-conversion mode requires the setting shown in Figure 18.5-3 . Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER ■ Operation of Pause-conversion Mode • When the start trigger is inputted, A/D conversion starts at the channel set by the A/D conversion start channel select bits (ANS3 to ANS0). The A/D conversion pauses at the termination of the A/D conversion for one channel. When the start trigger is inputted while A/D conversion pauses, A/D conversion for the next channel is performed.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.4 Conversion Using EI2OS Function The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using the EI2OS function. ■ Conversion Using EI2OS The use of the EI2OS enables the A/D-converted data protection function to transfer multiple data to memory without the loss of converted data even if A/D conversion is performed continuously. The conversion flow when the EI2OS is used is shown in Figure 18.5-4 . Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.5 A/D-converted Data Protection Function A/D conversion with the output of an interrupt request enabled activates the A/D conversion data protection function. ■ A/D-converted Data Protection Function in 8-/10-bit A/D Converter The 8-/10-bit A/D converter has only one A/D data register (ADCR) where A/D-converted data is stored. When the A/D conversion results are determined after the termination of A/D conversion, data in the A/D data register is rewritten.
CHAPTER 18 8-/10-BIT A/D CONVERTER Figure 18.
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.6 Precautions when Using 8-/10-bit A/D Converter Precautions when using the 8-/10-bit A/D converter are given below: ■ Precautions when Using 8-/10-bit A/D Converter ● Analog input pin • The analog input pins serve as general-purpose I/O ports of port 5 and port 6. When using the pin as an analog input pin, switch the pin to "analog input pin" according to the setting of the analog input enable register (ADER5 , ADER6).
CHAPTER 18 8-/10-BIT A/D CONVERTER 370
CHAPTER 19 LOW VOLTAGE DETECTION/ CPU OPERATING DETECTION RESET This chapter explains the function and operating the low voltage detection/CPU operating detection reset. This function can use only the product with "T" suffix of MB90360 series. 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register 19.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit The low voltage detection reset circuit watches the power-supply voltage and has the function to detect the power-supply voltages falling lower than the detection voltage values. When the low voltage is detected, internal reset is generated.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET ■ CPU Operating Detection Reset Circuit CPU operating detection reset circuit is a counter for preventing the program out of control. After power-on reset, it starts automatically. After it starts, it is necessary to keep clearing regularly within the fixed time. Internal reset is generated when not cleared during the fixed time by an program infinite loop, etc.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit Low voltage/CPU operating detection reset circuit has following three blocks. • CPU operating detection circuit • Voltage comparison circuit • Low voltage/CPU operating detection reset control register (LVRC) ■ Block Diagram of Low Voltage/CPU Operating Detection Reset Circuit Figure 19.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET ● CPU operating detection circuit It is a counter for preventing the program out of control. After it starts, it is necessary to keep clearing regularly within the fixed time. ● Voltage comparison circuit When the detection voltage is compared with the power-supply voltage, the output is set to "H" after the low voltage detection. After the power supply is turned on, it always operates.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register This register clears the low voltage/CPU operating detection reset flag and the counter of CPU operating detection circuit. ■ Low Voltage/CPU Operating Detection Reset Control Register (LVRC) Figure 19.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET Table 19.3-1 Functional Description of Low Voltage/CPU operating Detection Reset Control Register Bit name Function bit7/ bit6 Reserved: Reserved bits Note: These bits should write "0". bit5/ bit4 Reserved: Reserved bits Note: These bits should write "1". bit3 CL: CPU operating detection clear bit This bit is a bit that clears the counter of CPU operating detection circuit.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit The circuit watches the power-supply voltage. When the power supply voltage is lower than the set value, internal reset is generated. In CPU operating detecting function, internal reset is generated without the counter clear at constant intervals.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit This section explains the note on using the low voltage/CPU operating detection reset circuit. ■ Notes on Using Low Voltage Detection Reset Circuit ● Disabled operating stop from program The low voltage detection reset circuit operates continuously after the power supply is turned on and the operating stabilization wait time passes.
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit This section shows the sample program for low voltage/CPU operating detection reset circuit. ■ Sample Program for Low Voltage/CPU Operating Detection Reset Circuit ● Processing specification The counter of CPU operating detecting function is cleared.
CHAPTER 20 LIN-UART This chapter explains the functions and operation of LIN-UART. 20.1 Overview of LIN-UART 20.2 Configuration of LIN-UART 20.3 LIN-UART Pins 20.4 LIN-UART Registers 20.5 LIN-UART Interrupts 20.6 LIN-UART Baud Rates 20.7 Operation of LIN-UART 20.
CHAPTER 20 LIN-UART 20.1 Overview of LIN-UART The LIN-UART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization) with external devices. LIN-UART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LINbus systems.
CHAPTER 20 LIN-UART Table 20.1-1 LIN-UART Functions (2/2) Function LIN bus option • Master device operation Slave device operation • LIN Synch break detection • LIN Synch break generation • Detection of start/stop edges in LIN Synch field connected to input capture 0 and 1 • Synchronous serial clock Synchronous serial clock can be continuously outputted to SCK pin for synchronous communication with start/stop bits.
CHAPTER 20 LIN-UART ■ LIN-UART operation modes The LIN-UART operates in four different modes, which are determined by the MD0- and the MD1-bit of the serial mode register (SMR). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication. Table 20.
CHAPTER 20 LIN-UART ■ LIN-UART interrupt and EI2OS Table 20.
CHAPTER 20 LIN-UART 20.2 Configuration of LIN-UART This section provides a short overview on the building blocks of LIN-UART.
CHAPTER 20 LIN-UART ■ Block Diagram of LIN-UART Figure 20.
CHAPTER 20 LIN-UART ■ Explanation of the different blocks ● Reload Counter The reload counter is a 15-bit reload counter that functions as the dedicated baud rate generator. It can select external clock or internal clock for the transmitting and receiving clocks. The reload counter has a 15-bit register for the reload value. The actual count of the transmission reload counter can be read via the BGRn0/n1.
CHAPTER 20 LIN-UART ● Oversampling Circuit The oversampling circuit oversamples the incoming data at the SINn pin for five times in the asynchronous mode. The received value is determined by majority decision of sampling time. It is switched off in synchronous operation mode. ● Interrupt Generation Circuit The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a corresponding interrupt enable bit is set, the interrupt will be generated immediately.
CHAPTER 20 LIN-UART ● Serial Control Register (SCR) This register performs the following operations: • Specifying whether to provide parity bits • Selecting parity bits • Specifying a stop bit length • Specifying a data length • Selecting a frame data format in mode 1 • Clearing the error flags • Specifying whether to enable transmission • Specifying whether to enable reception ● Serial Status Register (SSR) This register performs the following functions; • Indicating status of receive/transmit operations
CHAPTER 20 LIN-UART 20.3 LIN-UART Pins This section describes the LIN-UART pins and provides a pin block diagram. ■ LIN-UART Pins The LIN-UART pins also serve as general ports. Table 20.3-1 lists the pin functions, I/O formats, and settings required to use LIN-UART. Table 20.
CHAPTER 20 LIN-UART 20.4 LIN-UART Registers The following figure shows the LIN-UART registers. ■ LIN-UART Registers Figure 20.
CHAPTER 20 LIN-UART 20.4.1 Serial Control Register (SCR) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. ■ Serial Control Register (SCR) Figure 20.
CHAPTER 20 LIN-UART Table 20.4-1 Function of Each Bit in Serial Control Register (SCR) No. Bit Name Function bit15 PEN: Parity enable bit This bit selects whether to add a parity bit during transmission or detect it during reception. Note: Parity bit is only provided in mode 0 and in mode 2 if SSM of the ECCR is selected to 1. This bit is fixed to 0 (no parity) in mode 3 (LIN).
CHAPTER 20 LIN-UART 20.4.2 LIN-UART Serial Mode Register (SMR) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. ■ LIN-UART Serial Mode Register (SMR) Figure 20.
CHAPTER 20 LIN-UART Table 20.4-2 Function of Each Bit in Serial Mode Register (SMR) No. Bit name Function bit7, bit6 MD1, MD0: Operation mode setting bits These two bits set the LIN-UART operation mode. bit5 OTO: One-to-one external clock input enable bit This bit sets an external clock directly to the LIN-UART serial clock by writing "1". This function is used for operating mode 2 (synchronous) slave mode operation (ECCR:MS=1). When EXT=0, this bit is fixed to "0".
CHAPTER 20 LIN-UART 20.4.3 Serial Status Register (SSR) This register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. ■ Serial Status Register (SSR) Figure 20.
CHAPTER 20 LIN-UART Table 20.4-3 Function of Each Bit in Serial Status Register (SSR) No.
CHAPTER 20 LIN-UART 20.4.4 Reception and Transmission Data Register (RDR/TDR) Both RDR and TDR registers are located at the same address. At reading, it functions as the reception data register. At writing, it functions as the transmission data register. ■ Reception Data Register (RDR) Figure 20.
CHAPTER 20 LIN-UART ■ Transmission Data Register (TDR) TDR is the data buffer register for serial data transmission. When data to be transmitted is written to the transmission data register (TDR) in transmission enable state (SCR: TXE=1), it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output pin (SOTn pin). If the data length is 7 bits, the uppermost bit (TDR: D7) is invalid data.
CHAPTER 20 LIN-UART 20.4.5 Extended Status/Control Register (ESCR) This register provides several LIN functions, direct access to the SINn and SOTn pins and setting of continuous clock output and sampling clock edge in LIN-UART synchronous clock mode. ■ Extended Status/control Register (ESCR) Figure 20.4-6 shows the Configuration of the extended status/control register (ESCR), and Table 20.4-4 shows the function of each bit. Figure 20.
CHAPTER 20 LIN-UART Table 20.4-4 Function in Each Bit of the Extended Status/control Register (ESCR) NO. Bit name Function bit15 LBIE: LIN synch break detection interrupt enable bit This bit enables/disables LIN synch break detection interrupt. When the LBD bit is set to 1 and this bit is "1", a interrupt is generated. This bit is fixed to "0" in operation mode 1 and 2. bit14 LBD: LIN synch break detected flag bit This bit goes 1 if a LIN synch break was detected in operating mode 3.
CHAPTER 20 LIN-UART 20.4.6 Extended Communication Control Register (ECCR) The extended communication control register (ECCR) provides bus idle detection, synchronous clock settings, and the LIN synch break generation. ■ Extended Communication Control Register (ECCR) Figure 20.4-7 shows the configuration of the extended communication control register (ECCR), and Table 20.4-6 shows the function of each bit. Figure 20.
CHAPTER 20 LIN-UART Table 20.4-6 Function of Each Bit in the Extended Communication Control Register (ECCR) NO. Bit name Function bit7 Unused bit This bit is unused bit. Reading bit is undefined. Always write "0". bit6 LBR: Lin Synch break Generating bit Writing a 1 to this bit generates a LIN synch break of the length selected by the LBL0/LBL1 bits of the ESCR, if operation mode 3 is selected. Setting to "0" in operation mode 0.
CHAPTER 20 LIN-UART 20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1) The baud rate generator registers set the division ratio for the serial clock. Also, the actual count of the transmission reload counter can be read. ■ Baud Rate Generator Register (BGRn0/n1) Figure 20.4-8 shows the configuration of the baud rate generator register (BGRn0/n1). Figure 20.
CHAPTER 20 LIN-UART 20.5 LIN-UART Interrupts LIN-UART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the reception data register (RDR), or a reception error occurs. • Transmission data is transferred from the transmission data register (TDR) to the transmission shift register and transmission is started. • A LIN break is detected.
CHAPTER 20 LIN-UART ● Reception Interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the serial status register (SSR) is set to "1": • Data reception is completed, i. e. the received data was transferred from the serial input shift register to the reception data register (RDR) and data can be read: RDRF • Overrun error, i. e. RDRF = 1 and RDR was not read by the CPU and next serial data is received: ORE • Framing error, i. e.
CHAPTER 20 LIN-UART ● LIN Synchronization Field Edge Detection Interrupts This paragraph is only relevant, if LIN-UART operates in mode 3 as a LIN slave. After LIN synch break detection, the internal signal is set to "1" at first falling edge of the LIN synch field and to "0" after fifth falling edge. When the internal signal is set in the capture side to be inputted to capture (ICV0/1) and to be detected both edges, the interrupt occurs if the capture interrupt is enabled.
CHAPTER 20 LIN-UART 20.5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: completion of reception (SSR: RDRF) and occurrence of a reception error (SSR: PE, ORE, or FRE). ■ Reception Interrupt Generation and Flag Set Timing The received data is stored in the RDR register if the first stop bit is detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2 (if SSM = 0).
CHAPTER 20 LIN-UART Figure 20.
CHAPTER 20 LIN-UART 20.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDR) to transmission shift register and transmission is started. ■ Transmission Interrupt Generation and Flag Set Timing When the data written to the TDR register is transferred to the transmission shift register and the transmission is started, next data to be written is enabled (SSR: TDRE=1).
CHAPTER 20 LIN-UART ■ Transmission interrupt request generation timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR: TIE=1), transmission interrupt is generated. Note: A transmission interrupt is generated immediately after the transmission interrupt is enabled (SSR: TIE=1) because the TDRE bit is set to 1 as its initial value. TDRE is a read-only bit that can be cleared only by writing new data to the transmission data register (TDR).
CHAPTER 20 LIN-UART 20.6 LIN-UART Baud Rates One of the following can be selected for the LIN-UART transmission/reception clock source: • Dedicated baud rate generator (Reload Counter) • Input external clock to baud rate generator (Reload Counter) • External clock (directly use SCKn pin input clock) ■ LIN-UART Baud Rate Selection The baud rate selection circuit is designed as shown below.
CHAPTER 20 LIN-UART Figure 20.
CHAPTER 20 LIN-UART 20.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the Baud Rate The both 15-bit reload counters are programmed by the baud rate generator registers 1, 0 (BGR1/BGR0). The following calculation formula should be used to set the desired baud rate: Reload Value: v = [Φ / b] - 1, where Φ is the machine clock, b the baud rate and [] gaussian brackets (mathematical rounding function).
CHAPTER 20 LIN-UART ■ Suggested division ratios for different machine speeds and baud rates The following settings are suggested for different MCU clock speeds and baud rates: Table 20.6-1 Suggested Baud Rates and Reload Values at Different Machine Speeds. 8 MHz Baud rate value 10 MHz dev. value 16 MHz dev. value 20 MHz dev. value 24 MHz dev. value dev.
CHAPTER 20 LIN-UART ■ Using external clock If the EXT bit of the SMR is set to 1, an external clock is selected, which has to be connected to the SCKn pin. The external clock is used in the same way as the internal clock to the baud rate generator. If One-to-one External Clock Input Mode (SMR: OTO=1) is selected the SCKn signal is directly connected to the LIN-UART serial clock inputs. This is needed for the LIN-UART synchronous mode 2 operating as slave device.
CHAPTER 20 LIN-UART 20.6.2 Restarting the Reload Counter The reload counter is a 15-bit reload counter that functions as dedicated baud rate generator. The transmission/reception clock is generated by the external or internal clock. Also, the count value of the transmission reload counter can be read by the baud rate generator register (BGR1, BGR0). ■ Function of Reload Counter The reload counter has the transmission and reception reload counters and functions as dedicated baud rate generator.
CHAPTER 20 LIN-UART Note: If LIN-UART is reset by setting SMR:UPCL to "1", the Reload Counters will restart too. • Automatic restart (reception reload counter only) In asynchronous LIN-UART mode, if a falling edge of a start bit is detected, the Reception Reload Counter is restarted. This is intended to synchronize the serial shift register to the incoming serial data stream.
CHAPTER 20 LIN-UART 20.7 Operation of LIN-UART LIN-UART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication. ■ Operation of LIN-UART ● Operation modes There are four LIN-UART operation modes: modes 0 to 3. As listed in Table 20.7-1 , an operation mode can be selected according to the communication method. Table 20.
CHAPTER 20 LIN-UART ■ Inter-CPU Connection Method External Clock One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected. For either connection method, the data length, whether to enable parity, and the synchronization method must be common to all CPUs. Select an operation mode as follows: • In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs.
CHAPTER 20 LIN-UART 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) When LIN-UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. ■ Operation in Asynchronous Mode ● Transfer data format Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level) and ends with at least one stop bit (high-level).
CHAPTER 20 LIN-UART Figure 20.
CHAPTER 20 LIN-UART ● Transmission operation If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is "1", transmission data is allowed to be written to the Transmission Data Register (TDR). When data is written, the TDRE flag goes "0".
CHAPTER 20 LIN-UART ● Stop bit 1- or 2-stop bit can be selected at the transmission. When 2-stop bit is selected, both stop bits is detected at the reception. When first stop bit is detected, the RDRF bit of SSR is "1". Then, when the start bit is not detected, the RBI bit of ECCR is set to "1", indicating no reception operation. ● Error detection In mode 0, the parity, overrun, and framing errors can be detected.
CHAPTER 20 LIN-UART 20.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for LIN-UART operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation mode 2) ● Transfer data format In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR) is 0.
CHAPTER 20 LIN-UART ● Clock supply: In operation mode 2, the number of clock cycles for the clock signal must be the same as the number of bits for the transmission and reception. If the start/stop bits are enabled, it must be matched the additional start/ stop bits. If the MS bit of the ECCR register is "0" (master mode) and the SCKE bit of the SMR register is "1" (serial clock output enabled), the consistent clock cycles are generated automatically.
CHAPTER 20 LIN-UART ● Communication: For initialization of the synchronous mode, following settings have to be done: Baud rate generator registers (BGR0/BGR1): Set the desired reload value for the dedicated baud rate reload counter.
CHAPTER 20 LIN-UART 20.7.3 Operation with LIN Function (Operation Mode 3) LIN-UART can be used either as LIN-Master or LIN-Slave. For this LIN function a special mode is provided. Setting the LIN-UART to mode 3 configures the data format to 8N1LSB-first format. ■ Operation in Asynchronous LIN Mode (Operation mode 3) ● LIN-UART as LIN master In LIN master mode, the master determines the baud rate of the whole bus, therefore slaves devices have to synchronize to the master.
CHAPTER 20 LIN-UART where a is the value of the ICU data register after the first interrupt where b is the value of the ICU data register after the second interrupt Note: As shown in the LIN slave mode, when the BGR value newly calculated by synch field generates ±15% or more baud rate error, do not set the baud rate. For the correspondence between other LIN-UARTs and ICUs, see "13.5 Explanation of Operation of 16bit Free-run Timer" and "13.6 Explanation of Operation of Input Capture".
CHAPTER 20 LIN-UART Figure 20.7-8 LIN-UART Behavior as Slave in LIN Mode Serial clock Serial input (LIN bus) LBR cleared by CPU LBD ICU input signal (LSYN) Synch break (at 14-bit setting) Synch field ● LIN bus timing Figure 20.
CHAPTER 20 LIN-UART 20.7.4 Direct Access to Serial Pins LIN-UART allows the user to directly access to the transmission pin (SOTn) or the reception pin (SINn). ■ LIN-UART Direct Pin Access The LIN-UART provides the ability for the software to access directly to serial input or output pin. The software can always monitor the incoming serial input pin (SINn) by reading the SIOP bit of the ESCR.
CHAPTER 20 LIN-UART 20.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in Figure 20.7-10 are required to operate LIN-UART in normal mode (operation mode 0 or 2). Figure 20.
CHAPTER 20 LIN-UART ● Communication procedure Communication starts at arbitrary timing from the transmission side when the transmission data is provided. When the transmission data is received at the reception side, ANS (per one byte in example) is returned periodically. Figure 20.7-12 shows an example of the bi-directional communication flowchart. Figure 20.
CHAPTER 20 LIN-UART 20.7.6 Master-Slave Communication Function (Multiprocessor Mode) LIN-UART communication with multiple CPUs connected in master-slave mode is available for both master or slave systems in the operation mode 1. ■ Master-slave Communication Function The settings shown in Figure 20.7-13 are required to operate LIN-UART in multiprocessor mode (operation mode 1). Figure 20.
CHAPTER 20 LIN-UART ● Function selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 20.73. Table 20.
CHAPTER 20 LIN-UART Figure 20.7-15 Master-slave Communication Flowchart (Master CPU) (Slave CPU) Start Start Set operation mode 1 Set operation mode 1 Set SINn pin as the serial data input pin. Set SOTn pin as the serial data output pin. Set SINn pin as the serial data input pin. Set SOTn pin as the serial data output pin. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set "1" in AD bit.
CHAPTER 20 LIN-UART 20.7.7 LIN Communication Function LIN-UART communication with LIN devices is available for both LIN master or LIN slave systems. ■ LIN-master-slave Communication Function The settings shown in the figure below are required to operate LIN-UART in LIN communication mode (operation mode 3). Figure 20.
CHAPTER 20 LIN-UART 20.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3) This section contains sample flowcharts for LIN-UART in LIN communication. ■ LIN-UART as LIN Master Device Figure 20.
CHAPTER 20 LIN-UART ■ LIN-UART as LIN slave device Figure 20.
CHAPTER 20 LIN-UART 20.8 Notes on Using LIN-UART Notes on using LIN-UART are given below. ■ Notes on Using LIN-UART ● Enabling operations In LIN-UART, the serial control register (SCR) has TXE (transmission) and RXE (reception) operation enable bits. Both, transmission and reception operations, must be enabled before the communication starts because they have been disabled as the default value (initial value). The operation can also be canceled by disabling these bits.
CHAPTER 20 LIN-UART predefined value. ● Bus idle function The bus idle function cannot be used in synchronous mode 2. ● AD bit (serial control register (SCR): address/data type select bit) Special care has to be taken when using the AD bit (Address-Data-Bit for multiprocessor mode 1) of the Serial Control Register. This bit is both a control and a flag bit, because writing to it sets the AD bit for transmission, whereas reading from it returns the last received AD bit.
CHAPTER 21 CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. 21.1 Features of CAN Controller 21.2 Block Diagram of CAN Controller 21.3 List of Overall Control Registers 21.4 Classifying CAN Controller Registers 21.5 Transmission of CAN Controller 21.6 Reception of CAN Controller 21.7 Reception Flowchart of CAN Controller 21.8 How to Use CAN Controller 21.9 Procedure for Transmission by Message Buffer (x) 21.10 Procedure for Reception by Message Buffer (x) 21.
CHAPTER 21 CAN CONTROLLER 21.1 Features of CAN Controller The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. ■ Features of CAN Controller • Conforms to CAN Specification Version 2.
21.2 Block Diagram of CAN Controller Figure 21.2-1 shows a block diagram of the CAN controller. ■ Block Diagram of CAN Controller Figure 21.
CHAPTER 21 CAN CONTROLLER 21.3 List of Overall Control Registers Following Table lists the register. ■ List of overall Control Registers Table 21.
Table 21.
CHAPTER 21 CAN CONTROLLER ■ List of Message Buffers (ID registers) Table 21.
Table 21.
CHAPTER 21 CAN CONTROLLER ■ List of Message Buffers (DLC registers and data registers) Table 21.
■ List of Message Buffer (data register) Table 21.
CHAPTER 21 CAN CONTROLLER 21.
21.4.1 Configuration of Control Status Register (CSR) This register indicates bus operation, node status, transmit output enable and transmit/ receive status. The lower 8-bit with the control status register (CSR) is prohibited from executing any bit manipulation instructions (Read-Modify-Write instructions). Only in the case of HALT bits unchanged (initialization of the macro instructions etc.), there is no problem even if any bit manipulation instructions is used.
CHAPTER 21 CAN CONTROLLER 21.4.2 Function of Control Status Register (CSR) The operating status of the register’s each bit is confirmed by following; • Setting "0" or "1" • Function control by writing • Read ■ Control Status Register (CSR-lower) Table 21.4-1 Function of Each Bit of the Control Status Register (CSR:L) Bit Name Function bit7 TOE: Transmit output enable bit This bit switches from a general-purpose I/O port to a transmit pin TX. When setting to 0: Functions as general-purpose I/O port.
■ Control status register (CSR-upper) Table 21.4-2 Function of Each Bit of the Control Status Register (CSR:H) Bit Name Function bit15 TS: Transmit status bit This bit indicates whether a message is being transmitted. At read: 0: Message not being transmitted 1: Message being transmitted This bit is set 0 even while error and overload frames are transmitted. bit14 RS: Receive status bit This bit indicates whether a message is being received.
CHAPTER 21 CAN CONTROLLER 21.4.3 Correspondence between Node Status Bit and Node Status Node status bit shows the node status by two bits (NS1 and NS0). ■ Correspondence between Node Status Bit and Node Status Table 21.4-3 Correspondence between NS1 and NS0 and Node Status NS1 NS0 Node status 0 0 Error active 0 1 Warning (error active) 1 0 Error passive 1 1 Bus off Note: Warning (error active) is included in the error active in CAN Specification 2.
21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1) The bus operation stop bit is set by writing to the bit, hardware reset and the node status. The stop operation of the bus operation is different according to the state of the message buffer.
CHAPTER 21 CAN CONTROLLER 21.4.5 Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to 1, other bits are set to 0. ■ Last Event Indicator Register (LEIR) Figure 21.
■ Last Event Indicator Register (LEIR) Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (1 / 2) Bit Name Function bit7 NTE: Node status transition event bit When this bit is 1, node status transition is the last event. This bit is set to 1 after set either of bit of the control status register to "1" (CSR:NTx=1). • This setting is not related to the setting of NIE bit of the control status register (CSR).
CHAPTER 21 CAN CONTROLLER Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (2 / 2) Bit Name bit3 to bit0 460 MBP3 to MBP0: Message buffer pointer bits Function When TCE bit or RCE bit is "1", these bits show the message buffer number (x) to generating of corresponding the last event. If the NTE bit is set to 1, these bits have no meaning. At Write: "0": Cleared "1": No effect At read by the instruction of the read-modify-write type: Always read "1".
21.4.6 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read. ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER 21.4.7 Bit Timing Register (BTR) Bit timing register (BTR) sets the prescaler and bit timing setting. ■ Register Configuration Figure 21.4-6 Configuration of the Bit Timing Register (BTR) Address CAN1: 007D07H Address CAN1: R/W : X: −: 007D06H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 − TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.
21.4.8 Prescaler Setting by Bit Timing Register (BTR) The setting of bit timing register (BTR) corresponds to the bit time of prescaler in the CAN specification and the CAN controller segment. ■ Prescaler Settings The bit time segments defined in the CAN specification, and the CAN controller are shown in Figure 21.4-7 and Figure 21.4-8 respectively. Figure 21.4-7 Bit Time Segment in CAN Specification Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample point Figure 21.
CHAPTER 21 CAN CONTROLLER The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS2.0, and RSJ = RSJ1, RSJ0 TQ BT = (PSC + 1) x CLK = SYNC_SEG + TSEG1 + TSEG2 = (1 + (TS1 + 1) + (TS2 +1)) x TQ = (3 + TS1 +TS2) x TQ RSJW = (RSJ + 1) x TQ RSJ1 and RSJ0 is shown below.
21.4.9 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) stores the validity of the message buffers or displays their state. ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER 21.4.10 IDE Register (IDER) This register stores the frame format used by the message buffers (x) during transmission/reception. ■ Register Configuration Figure 21.
21.4.11 Transmission Request Register (TREQR) Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state. ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER 21.4.12 Transmission RTR Register (TRTRR) This register stores the RTR (Remote Transmission Request) bits for the message buffers (x). ■ Register Configuration Figure 21.
21.4.13 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) sets the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmitting RTR register (TRTRR) is 0). ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER 21.4.14 Transmission Cancel Register (TCANR) This register cancels a pending request for transmission to the message buffer (x). ■ Register Configuration Figure 21.
21.4.15 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes 1. If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs. ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER 21.4.16 Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is 1). ■ Register Configuration Figure 21.
21.4.17 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes 1. If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt occurs. ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER 21.4.18 Remote Request Receiving Register (RRTRR) After a remote frame is stored in the message buffer (x), RRTRx becomes 1 (at the same time as RCx setting to 1). ■ Register Configuration Figure 21.
21.4.19 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is 1 when completing storing of a received message in the message buffer (x), ROVRx becomes 1, indicating that reception has overrun. ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER 21.4.20 Reception Interrupt Enable Register (RIER) Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is 1). ■ Register Configuration Figure 21.
21.4.21 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the received message ID’s and the message buffer ID. ■ Register Configuration Figure 21.4-21 Configuration of the Acceptance Mask Select Register (AMSR) Address CAN1: 007D10H Address CAN1: 007D11H Address CAN1: 007D12H Address CAN1: 007D13H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMS3.1 AMS3.0 AMS2.1 AMS2.0 AMS1.1 AMS1.0 AMS0.1 AMS0.
CHAPTER 21 CAN CONTROLLER ■ Register Function Table 21.4-7 Selection of Acceptance Mask AMSx.1 AMSx.0 Acceptance Mask 0 0 Full-bit comparison 0 1 Full-bit mask 1 0 Acceptance mask register 0 (AMR0) 1 1 Acceptance mask register 1 (AMR1) Notes: • AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored.
21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) There are two acceptance mask registers, which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format. ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER Figure 21.
21.4.23 Message Buffers There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). ■ Message Buffers ● Register Configuration • ID register x (x = 0 to 15) (IDRx) This register is a ID register of the message buffer. This register memorizes receipt code setting, transmission message ID setting, and reception ID. • DLC register x (x = 0 to 15) (DLCRx) This register stores the DLC of the message buffer.
CHAPTER 21 CAN CONTROLLER ● Message buffer that can be used as multi level message buffer When the same receipt filter is set in 1 or more message buffers, the message buffer can be used as a multi level message buffer. As a result, the reserve to the reception time is given. (See "21.10 Procedure for Reception by Message Buffer (x)"). Notes: • A write operation to message buffers and general-purpose RAM areas should be performed in words to even addresses only.
21.4.24 ID Register x (x = 0 to 15) (IDRx) This register is the ID register for message buffer (x). ■ Register Configuration Figure 21.
CHAPTER 21 CAN CONTROLLER ■ Register Function When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0. ID28 to ID0 have the following functions; • Set acceptance code (ID for comparing with the received message ID). • Set transmitted message ID. Note: In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited).
21.4.25 DLC Register x (x = 0 to 15) (DLCRx) This register is the DLC register for message buffer (x). ■ Register Configuration Figure 21.4-25 Configuration of the DLC Registers (DLCRx) Address CAN1: 007C60H + 2 × x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 − − − − DLC3 DLC2 DLC1 DLC0 − − − − R/W R/W R/W R/W DLCR1x(Lower) Reset value XXXXXXXXB x = 0, ...
CHAPTER 21 CAN CONTROLLER 21.4.26 Data Register x (x = 0 to 15) (DTRx) This register is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame. ■ Register Configuration Figure 21.
■ Register Function ● Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. ● Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined. Note: A write operation to this register should be performed in words.
CHAPTER 21 CAN CONTROLLER 21.5 Transmission of CAN Controller When 1 is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes 1 and TCx of the transmission complete register (TCR) becomes 0. ■ Starting Transmission of CAN Controller If RFWTx of the remote frame receiving wait register (RFWTR) is 0, transmission starts immediately.
■ Completing Transmission of CAN Controller When transmission is successful, RRTRx becomes 0, TREQx becomes 0, and TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. ■ Transmission Flowchart of CAN Controller Figure 21.
CHAPTER 21 CAN CONTROLLER 21.6 Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. ■ Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is 0). The received message in the extended frame format is compared with the message buffer (x) set (IDEx is 1) in the extended frame format.
Figure 21.6-1 shows a flowchart for determining the message buffer (x) where received messages are to be stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits Mask. Figure 21.6-1 Flowchart Determining Message Buffer (x) where Received Messages Stored Start Are message buffers with RCx set to 0 or with AMSx.
CHAPTER 21 CAN CONTROLLER ■ Completing Reception RCx of the reception complete register (RCR) becomes 1 after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself.
21.7 Reception Flowchart of CAN Controller Figure 21.7-1 shows a reception flowchart of the CAN controller. ■ Reception Flowchart of the CAN Controller Figure 21.7-1 Reception Flowchart of the CAN Controller Detection of start of data frame or remote frame (SOF) NO Is any message buffer (x) passing to the acceptance filter found? YES NO Is reception successful? YES Determine message buffer (x) where received messages to be stored. Store the received message in the message buffer (x).
CHAPTER 21 CAN CONTROLLER 21.8 How to Use CAN Controller The following settings are required to use the CAN controller; • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode ■ Setting Bit Timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is 1). After the setting completion, write 0 to HALT to cancel bus operation stop.
■ Setting Low-power Consumption Mode To set the F2MC-16LX in a low-power consumption mode (Stop and Timebase timer), write 1 to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1).
CHAPTER 21 CAN CONTROLLER 21.9 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to 1 to activate the message buffer (x). ■ Procedure for Transmission by Message Buffer (x) ● Setting transmit data length code Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx).
● Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to 0 to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmission RTR register (TRTRR) is 0).
CHAPTER 21 CAN CONTROLLER 21.10 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. ■ Procedure for Reception by Message Buffer (x) ● Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to 1. To disable reception interrupt, set RIEx to 0.
Figure 21.10-1 Example of Receive Interrupt Handling Interrupt with RCx = 1 Read received messages.
CHAPTER 21 CAN CONTROLLER 21.11 Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID’s of messages are received, in other words, if there is insufficient time for handling messages, more than 1 message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU.
Figure 21.11-1 Examples of Operation of Multi-level Message Buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 Select AMR0. ... AM28 to AM18 AMS0 ID28 to ID18 0000 1111 111 RC15, RC14, RC13 IDE ... Message buffer 13 0101 0000 000 0 ... RCR 0 0 0 ... Message buffer 14 0101 0000 000 0 ... ROVRR 0 0 0 ... Message buffer 15 0101 0000 000 0 ... ROVR15, ROVR14, ROVR13 Mask Message receiving: The received message is stored in message buffer 13.
CHAPTER 21 CAN CONTROLLER 21.12 Setting the CAN Direct Mode Register To operate CAN normally, this register must be set correctly. ■ CAN Direct Mode Register (CDMR) (Only MB90V340) Figure 21.12-1 Configuration of the CAN Direct Mode Register (CDMR) (Only MB90V340) Address: 7 6 5 4 3 2 1 CAN0: 00796EH - - - - - - - - - - - - - - R/W 0 DIRECT CDMR Initial value XXXXXXX0 B R/W : Readable and writable X : Undefined value : Undefined Table 21.
21.13 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. ■ Caution for Disabling Message Buffers by BVAL Bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication. This section shows the work around of this malfunction. ● Condition When following 2 conditions occur at the same time, the CAN Controller will not perform to transmit messages normally.
CHAPTER 21 CAN CONTROLLER ■ Setting of CAN Direct Mode MB90360 does not provide the clock modulation function. For this reason, ensure that the DIRECT bit of the CAN direct mode register (CDMR) is set to 1 when CAN is used. Note that the CAN controller will not normally operate without correct setting of the DIRECT bit.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and its operation. 22.1 Overview of Address Match Detection Function 22.2 Block Diagram of Address Match Detection Function 22.3 Configuration of Address Match Detection Function 22.4 Explanation of Operation of Address Match Detection Function 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.1 Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detect address setting registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR0/PACSR1) • Detect address setting registers (PADR0 to PADR5) ■ Block Diagram of Address Match Detection Function Figure 22.2-1 shows the block diagram of the address match detection function. Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 Configuration of Address Match Detection Function This section lists and details the registers used by the address match detection function. ■ List of Registers and Reset Values of Address Match Detection Function Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3.1 Address Detection Control Register (PACSR0/PACSR1) The address detection control register enables or disables output of an interrupt at an address match. When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. ■ Address Detection Control Register 0 (PACSR0) Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Table 22.3-1 Functions of Address Detection Control Register (PACSR0) Bit Name 510 Function bit7, bit6 Reserved: reserved bits Always set to 0. bit5 AD2E: Address match detection enable bit 2 The address match detection operation with the detect address setting register 2 (PADR2) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Address Detection Control Register 1 (PACSR1) Figure 22.3-3 Address Detection Control Register 1 (PACSR1) Address 15 14 Re- Re0 0 0 0 3 B H served served 13 12 11 10 9 8 ReReReAD5E served AD4E served AD3E served R/W R/W R/W R/W R/W R/W R/W R/W Reset value 00000000B bit 8 Reserved bit Reserved 0 Always set to "0". bit 9 AD3E Address match detection enable bit 3 0 Disables address match detection in PADR3.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Table 22.3-2 Functions of Address Detection Control Register (PACSR1) Bit Name 512 Function bit15, bit14 Reserved: reserved bit Always set to 0. bit13 AD5E: Address match detection enable bit 5 The address match detection operation with the detect address setting register 5 (PADR5) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3.2 Detect Address Setting Registers (PADR0 to PADR5) The value of an address to be detected is set in the detect address setting registers. When the address of the instruction processed by the program matches the address set in the detect address setting registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed. ■ Detect Address Setting Registers (PADR0 to PADR5) Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Functions of Detect Address Setting Registers • There are six detect address setting registers (PADR0 to PADR5) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0 to PADR5), the address match detection function will replace the first instruction code executed by the CPU with the INT9 instruction (01H) to branch to the interrupt processing program. ■ Operation of Address Match Detection Function Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4.1 Example of using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. ■ System Configuration and E2PROM Memory Map ● System configuration Figure 22.4-2 gives an example of the system configuration using the address match detection function. Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ E2PROM Memory Map Figure 22.4-3 shows the allocation of the patch program and data at storing the patch program in E2PROM. Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Setting and Operating State ● Initialization E2PROM data are all cleared to "00H". ● Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU (F2MC16LX) from the outside according to the allocation of the E2PROM patch program and data. • The MCU (F2MC16LX) stores the information received from outside in the E2PROM.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ■ Operation of Address Match Detection Function at Storing Patch Program in E2PROM Figure 22.4-4 shows the operation of the address match detection function at storing the patch program in E2PROM. Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Figure 22.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. ■ Program Example for Address Match Detection Function ● Processing specifications If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION .
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 524
CHAPTER 23 ROM MIRRORING MODULE This chapter describes the functions and operations of the ROM mirroring function select module. 23.1 Overview of ROM Mirroring Function Select Module 23.
CHAPTER 23 ROM MIRRORING MODULE 23.1 Overview of ROM Mirroring Function Select Module The ROM mirroring function select module provides a setting so that ROM data in the FF bank can be read by access to the 00 bank. ■ Block Diagram of ROM Mirroring Function Select Module Figure 23.
CHAPTER 23 ROM MIRRORING MODULE ■ Memory Space when ROM Mirroring Function Enabled/Disabled Figure 23.1-3 shows the availability of access to memory space when the ROM mirroring function is enabled or disabled. Figure 23.
CHAPTER 23 ROM MIRRORING MODULE 23.2 ROM Mirroring Function Select Register (ROMM) The ROM mirroring function select register (ROMM) enables or disables the ROM mirroring function. When the ROM mirroring function is enabled, ROM data in the FF bank can be read by access to the 00 bank. ■ ROM Mirroring Function Select Register (ROMM) Figure 23.
CHAPTER 24 512K-BIT FLASH MEMORY This chapter explains the functions and operation of the 512K-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer • Executing programs to write/erase data This chapter explains “Executing programs to write/ erase data”. 24.1 Overview of 512K-bit Flash Memory 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.1 Overview of 512K-bit Flash Memory The 512K-bit flash memory is mapped to the FFH bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted.
CHAPTER 24 512K-BIT FLASH MEMORY 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory Figure 24.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 24.2-2 shows the sector configuration of the flash memory. ■ Block Diagram of the Entire Flash Memory Figure 24.
CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.2-2 Sector Configuration of the 512K-bit Flash Memory MB90F362/T(S), MB90F367/T(S) Programmer address* CPU address 7FFFFH FFFFFFH 70000H FF0000H SA0 (64K bytes) *: The programmer address is equivalent to the CPU address when data is written to the flash memory using a parallel programmer. When a general programmer is used for writing/erasing, this address is used for writing/erasing.
CHAPTER 24 512K-BIT FLASH MEMORY 24.3 Write/Erase Modes The flash memory can be accessed in 2 different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus. Use the mode external pins to select the mode. ■ Flash Memory Mode The CPU stops when the mode pins are set to "111B" while the reset signal is asserted.
CHAPTER 24 512K-BIT FLASH MEMORY Table 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.4 Flash Memory Control Status Register (FMCS) This section shows the function of the flash memory control status register (FMCS). ■ Flash Memory Control Status Register (FMCS) Figure 24.
CHAPTER 24 512K-BIT FLASH MEMORY Table 24.4-1 Functions of Control Status Register (FMCS) Bit Name Function bit7 INTE: Flash memory programming/erasing interrupt enable bit This bit enables or disables an interrupt as programming/erasing flash memory is terminated. When set to 1: If the flash memory operation flag bit is set to 1 (FMCS: RDYINT=1), an interrupt is requested. bit6 RDYINT: Flash memory operation flag bit This bit shows the operating state of flash memory.
CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.5 Starting the Flash Memory Automatic Algorithm Three types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. ■ Command Sequence Table Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write. The data of the high-order bytes at this time is ignored. Table 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences flag.
CHAPTER 24 512K-BIT FLASH MEMORY To determine whether automatic writing or chip erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control status register (FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic writing/erasing has terminated.
CHAPTER 24 512K-BIT FLASH MEMORY 24.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated ■ Data Polling Flag (DQ7) Table 24.6-3 and Table 24.6-4 list the state transitions of the data polling flag. Table 24.6-3 State Transition of Data Polling Flag (State change at normal operation) Operating State Programming → Completed Chip Erasing → Completed DQ7 DQ7 → DATA:7 0→1 Table 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.6.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Toggle Bit Flag (DQ6) Table 24.6-5 and Table 24.6-6 list the state transitions of the toggle bit flag. Table 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Timing Limit Exceeded Flag (DQ5) Table 24.6-7 and Table 24.6-8 list the state transitions of the timing limit exceeded flag. Table 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase when a command that starts the automatic algorithm is issued. ■ Detailed Explanation of Flash Memory Write/erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 24.5-1 ) for a write cycle to the bus to perform Read/Reset, Write, or Chip Erase operations.
CHAPTER 24 512K-BIT FLASH MEMORY 24.7.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the Flash Memory to the Read/reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory.
CHAPTER 24 512K-BIT FLASH MEMORY 24.7.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. ■ Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory.
CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.7.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. ■ Erasing all Data in the Flash Memory (Erasing chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory. The Chip Erase command is executed in six bus operations.
CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.
CHAPTER 24 512K-BIT FLASH MEMORY 24.8 Notes on Using 512K-bit Flash Memory This section contains notes on using 512K-bit flash memory. ■ Notes on Using Flash Memory ● Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum "L" level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated.
CHAPTER 24 512K-BIT FLASH MEMORY 24.9 Flash Security Feature Flash security feature provides possibilities to protect the content of the flash memory. ■ Abstract By writing the protection code of "01H" to the security bit in the flash memory, access to the flash memory is restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the function. Otherwise, read/write access to the flash memory from the external pins is not possible.
CHAPTER 24 512K-BIT FLASH MEMORY 552
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/AF210/AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation when the AF220/AF210/AF120/ AF110 flash serial microcontroller programer from Yokogawa Digital Computer Corporation is used. 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) 25.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) The MB90F362/T(S), MB90F367/T(S) supports on-board writing (Fujitsu standard) of the flash ROM. This section provides the related specifications.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION Table 25.1-1 Pin Used for Fujitsu Standard Serial on-board Programming Pin Function Additional information MD2, MD1, MD0 Mode pins Controls programming mode from the flash microcontroller programmer. X0, X1 Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION programmer) Table 25.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.2 Example of Serial Programming Connection (User Power Supply Used) Figure 25.2-1 shows an example of a serial programming connection when the user power supply is used. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110. ■ Example of Serial Programming Connection (User power supply used) Figure 25.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P83. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.3 Example of Serial Programming Connection (Power Supplied from Programmer) Figure 25.3-1 shows an example of a serial programming connection when power is supplied from the programmer. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P83. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) Figure 25.4-1 shows an example of the minimum connection to the flash microcontroller programmer when the user power supply is used. Serial reprogramming mode: MD2, MD1, MD0 = 110.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer) Figure 25.5-1 shows an example of the minimum connection to the MB90F362/T(S), MB90F367/T(S) flash microcontroller programmer when power is supplied from the Programmer. Serial reprogramming mode: MD2, MD1, MD0 = 110B.
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) Figure 25.
CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function. 26.
CHAPTER 26 ROM SECURITY FUNCTION 26.1 Overview of ROM Security Function The ROM security function protects the content of ROM. ■ Overview of ROM Security Function The ROM security function is a function to prevent ROM data being read to the third party by limiting the access to ROM. Please contact to Fujitsu about details of this function.
APPENDIX The appendixes provide I/O maps, instructions, and other information.
APPENDIX APPENDIX A I/O Maps Table A-1 lists addresses to be assigned to the registers in the peripheral blocks.
APPENDIX A I/O Maps Table A-1 I/O Map (2/5) Address Register 000019H Reserved 00001AH Port A direction register 00001BH to 00001DH Reserved 00001EH Port 2 pull-up control register 00001FH Reserved 000020H Abbreviation Access Peripheral Initial value DDRA W Port A XXX0 0XXXB PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B Serial mode register 0 SMR0 W, R/W 0 0 0 0 0 0 0 0B 000021H Serial control register 0 SCR0 W, R/W 0 0 0 0 0 0 0 0B 000022H Reception/transmission data register 0 RDR0
APPENDIX Table A-1 I/O Map (3/5) Address Register Abbreviation Access 00004BH Reserved 00004CH PPGE operation mode control register PPGCE W, R/W 00004DH PPGF operation mode control register PPGCF W, R/W 00004EH PPGE/F count clock selection register PPGEF R/W 00004FH Reserved 000050H Input capture control status 0/1 000051H Input capture edge 0/1 ICE01 R/W, R 000052H Input capture control status 2/3 ICS23 R/W 000053H Input capture edge 2/3 000054H to 000063H Reserved 000064H
APPENDIX A I/O Maps Table A-1 I/O Map (4/5) Address Register Abbreviation Access Peripheral Initial value Delayed Interrupt XXXXXXX0B Generation Module 00009FH Delayed interrupt/release register DIRR R/W 0000A0H Low-power mode control register LPMCR W, R/W Low Power Controller 0 0 0 1 1 0 0 0B 0000A1H Clock selection register CKSCR R, R/W Low Power Controller 1 1 1 1 1 1 0 0B 0000A2H to 0000A7H Reserved 0000A8H Watchdog timer control register WDTC R, W Watchdog Timer XXXXX111B
APPENDIX Table A-1 I/O Map (5/5) Address Register Abbreviation Access Peripheral Initial value 0000CAH External interrupt enable 1 ENIR1 R/W 0 0 0 0 0 0 0 0B 0000CBH External interrupt request 1 EIRR1 R/W XXXXXXXXB 0000CCH External interrupt level 1 ELVR1 R/W External Interrupt 1 0 0 0 0 0 0 0 0B 0000CDH External interrupt level 1 ELVR1 R/W 0 0 0 0 0 0 0 0B 0000CEH External interrupt 1 source select EISSR R/W 0 0 0 0 0 0 0 0B 0000CFH PLL/subclock control register PSCCR W
APPENDIX A I/O Maps ■ I/O map (79XX - 7FXX addresses) Table A-2 I/O Map (7900H - 7FFFH) (1/3) Address Register Abbreviation Access Peripheral Initial value 7900H to 7917H Reserved 7918H Reload register LC PRLLC R/W 7919H Reload register HC PRLHC R/W 791AH Reload register LD PRLLD R/W 791BH Reload register HD PRLHD R/W XXXXXXXXB 791CH Reload register LE PRLLE R/W XXXXXXXXB 791DH Reload register HE PRLHE R/W 791EH Reload register LF PRLLF R/W 791FH Reload register HF
APPENDIX Table A-2 I/O Map (7900H - 7FFFH) (2/3) Address Register 7950H to 795FH Reserved 7960H Clock supervisor control register 7961H to 796DH Reserved 796EH CAN direct mode register (For only MB90V340) 796FH to 79DFH Reserved 79E0H Abbreviation Access Peripheral Initial value CSVCR R, R/W Clock supervisor 0 0 0 1 1 1 0 0B CDMR R/W CAN Clock Sync XXXXXXX0B Detection address setting 0 PADR0 R/W XXXXXXXXB 79E1H Detection address setting 0 PADR0 R/W XXXXXXXXB 79E2H Detecti
APPENDIX A I/O Maps Table A-2 I/O Map (7900H - 7FFFH) (3/3) Address Register Abbreviation Access Peripheral 7D00H to 7DFFH Reserved for CAN interface 1. (For more information, see Table 21.3-2 .) 7E00H to 7FFFH Reserved Initial value Note: Any write access to reserved addresses in I/O map should not be perfoermed. A read access to reserved address results in reading "X".
APPENDIX APPENDIX B Instructions Appendix B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.
APPENDIX B Instructions B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself.
APPENDIX B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing.
APPENDIX B Instructions ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.
APPENDIX B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.
APPENDIX B Instructions Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose register R0.) Before execution A 0716 2534 After execution A 0716 2564 Memory space R0 ?? Memory space R0 34 ● Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space.
APPENDIX ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.
APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir) MOVW S;20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.
APPENDIX ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB I:0C1H:0 (This instruction sets bits by I/O direct bit addressing.
APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.
APPENDIX B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address.
APPENDIX B Instructions Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.
APPENDIX ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB).
APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-Kbyte bank. This addressing is used for both conditional and unconditional branch instructions.
APPENDIX Figure B.4-9 Example of Register List (rlst) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.
APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.
APPENDIX ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.
APPENDIX B Instructions B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch.
APPENDIX ■ Calculating the execution cycle count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode (a) * Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Register access count in each addressing mode See the instruction list. See the instruction list.
APPENDIX B Instructions Table B.
APPENDIX B.6 Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.
APPENDIX B Instructions B.7 How to Read the Instruction List Table B.7-1 describes the items used in the F2MC-16LX Instruction List, and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Description Mnemonic Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler.
APPENDIX Table B.7-1 Description of Items in the Instruction List (2/2) Item RMW Description Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.
APPENDIX B Instructions Table B.
APPENDIX B.8 F2MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. ■ F2MC-16LX Instruction List Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.
APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction code Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map] (*1) UV +W *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions.
616 2-byte instruction Character string operation instruction Bit operation instruction Ri,ea ea instruction 9 ea instruction 8 ea instruction 7 ea instruction 6 ea instruction 5 ea instruction 4 ea instruction 3 ea instruction 2 ea instruction 1 APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions A A DIVU MULW MUL A Table B.
620 Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX Table B.
APPENDIX B Instructions Table B.
APPENDIX APPENDIX C Timing Diagrams in Flash Memory Mode Each timing diagram for the external pins of the Flash devices in MB90360 series during Flash Memory mode is shown below.
APPENDIX C Timing Diagrams in Flash Memory Mode ■ Write, Data Polling, Read (WE control) Figure C-2 Write, Data Polling, Read (WE control) Data polling 3rd bus cycle AQ18 to AQ0 FxAAAAH PA tAS tWC PA tAH tRC CE tCH tCS tCE OE tWP tWHWH1 tOE tGHWL WE tWPH tDS tDH DQ7 to DQ0 PA PD DQ7 DOUT A0H tDF PD DQ7 DOUT tOH DOUT : Write address : Write data : Reverse output of write data : Output of write data Note: • Describes the last 2-bus cycle of 4-bus cycle sequences.
APPENDIX ■ Write, Data Polling, Read (CE control) Figure C-3 Timing Diagram for Write Access (CE control) 3rd bus cycle AQ18 to AQ0 Data polling PA FxAAAAH tWC tAS PA tAH tWH WE tGHWL OE tCP tWHWH1 CE tCPH tWS tDH A0H DQ7 to DQ0 PD tDS PA PD DQ7 DOUT : Write address : Write data : Reverse output of write data : Output of write data Note: • Describes the last 2-bus cycle of 4-bus cycle sequences. • "Fx" in "FxAAAA" described as address is any of F.
APPENDIX C Timing Diagrams in Flash Memory Mode ■ Chip Erase/sector Erase Command Sequence Figure C-4 Timing Diagram for Write Access (chip erasing/sector erasing) tAS AQ18 to AQ0 FxAAAAH tAH Fx5555H FxAAAAH FxAAAAH SA* Fx5555H CE tGHWL OE tWP WE tWPH tCS tDH AAH DQ7 to DQ0 55H 80H AAH 55H 10H/30H tDS VCC tVCS Notes: • SA is the sector address at erasing sector. • The address is FxAAAAH at erasing sector. • "Fx" in "FxAAAA" described as address is any of F.
APPENDIX ■ Data Polling Figure C-5 Timing Diagram for Data Polling tCH CE tOE tDF OE tOEH WE tCE DQ7 tOH DQ7 = valid data DQ7 High-Z tWHWH1 or tWHWH2 DQ6 to DQ0 DQ6 to DQ0 flag output DQ6 to DQ0 = valid data tOE Note: DQ7 is valid data (The device terminates automatic operation).
APPENDIX C Timing Diagrams in Flash Memory Mode ■ RY/BY Timing during Writing/erasing Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/erasing CE Rising edge of last write pulse WE Writing or erasing RY/BY tBUSY ■ RST and RY/BY Timing Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset CE RY/BY tRP RST tReady 641
APPENDIX ■ Enable Sector Protect/verify Sector Protect Figure C-9 Enable Sector Protect/verify Sector Protect AQ18 to AQ9 SAX SAY (AQ8, AQ2, AQ1) = (0, 1, 0) AQ8, AQ2, AQ1 MD0 12 V 5V MD2 12 V 5V tVLHT tVLHT OE tWPP WE tOESP tCSP CE DQ7 to DQ0 01H tOE SAX: First sector address SAY: Next sector address 642
APPENDIX C Timing Diagrams in Flash Memory Mode ■ Temporary Sector Protect Cancellation Figure C-10 Temporary Sector Protect Cancellation MD1 12 V 5V 5V CE WE tVLHT Write/erase command sequence RY/BY 643
APPENDIX APPENDIX D List of Interrupt Vectors The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00H to FFFFFFH in the memory area and also used for software interrupts. ■ List of Interrupt Vectors Table D-1 lists the interrupt vectors for the MB90360 series.
APPENDIX D List of Interrupt Vectors Table D-1 Interrupt Vectors (2/2) Interrupt request INT 31 Interrupt cause Interrupt control register Vector address Vector address Vector address Mode register L H bank Number Address Reserved ICR10 INT 32 Reserved INT 33 Input capture 0 to 3 ICR11 INT 34 Reserved INT 35 UART 0 RX ICR12 INT 36 UART 0 TX INT 37 UART 1 RX ICR13 INT 38 UART 1 TX INT 39 Reserved ICR14 INT 40 Reserved INT 41 Flash Memory ICR15 0000BAH 0000BBH 0000BCH 0000BDH 0000
APPENDIX ■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control registers of the MB90360 series.
APPENDIX D List of Interrupt Vectors Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2) Interrupt cause EI2OS clear DMA channel number Interrupt vector Number UART 1 RX Y2 #37 FFFF68H UART 1 TX Y1 #38 FFFF64H Reserved N #39 FFFF60H Reserved N #40 FFFF5CH Flash memory N #41 FFFF58H Delayed interrupt generation module N #42 FFFF54H Interrupt control register ICR Address ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Y1: An EI2OS interrupt clear
APPENDIX 648
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
INDEX Index Numerics 16-bit Free-run Timer Block Diagram of 16-bit Free-run Timer ............213 Explanation of Operation of 16-bit Free-run Timer .......................................................... 229 16-bit I/O Timer 16-bit I/O Timer Interrupt and EI2OS ................. 228 Block Diagram of 16-bit I/O Timer .................... 211 Functions of 16-bit I/O Timer............................ 210 Generation of Interrupt Request from 16-bit I/O Timer ................................................
INDEX A A Accumulator (A) ................................................ 40 A/D Control Status Register A/D Control Status Register (High) (ADCS1)..... 346 A/D Control Status Register (Low) (ADCS0) ..... 349 A/D Converter 8-/10-bit A/D Converter Interrupt and EI2OS...... 358 A/D-converted Data Protection Function in 8-/10-bit A/D Converter....................... 367 Block Diagram of 8-/10-bit A/D Converter......... 341 Conversion Modes of 8-/10-bit A/D Converter ...........................................
INDEX Bidirectional Communication Bidirectional Communication Function .............. 433 Bit Timing Setting Bit Timing............................................494 Block Diagram Block Diagram of 16-bit Free-run Timer ............213 Block Diagram of 16-bit I/O Timer .................... 211 Block Diagram of 16-bit Reload Timer............... 240 Block Diagram of 8-/10-bit A/D Converter ......... 341 Block Diagram of 8-/16-bit PPG Timer C........... 286 Block Diagram of 8-/16-bit PPG Timer D...........
INDEX Clock Supervisor Control Register Clock Supervisor Control Register (CSVCR)...... 113 Clock Supply Cycle of Clock Supply...................................... 269 Clocks Clocks............................................................... 92 CMR Common Register Bank Prefix (CMR)................. 49 Command Sequence Chip Erase/sector Erase Command Sequence...... 639 Command Sequence Table................................ 538 Common Register Bank Prefix Common Register Bank Prefix (CMR).................
INDEX Data Polling Flag Data Polling Flag (DQ7) ................................... 541 Data Read Data Read by Read Access................................ 636 Data Register List of Message Buffer (data register)................. 451 List of Message Buffers (DLC registers and Data registers) ........ 450 DCT Data Counter (DCT) ........................................... 76 DDR Port Direction Register (DDR)...........................
INDEX Correspondence between 16-bit Reload Timer Interrupt and EI2OS............................. 251 Correspondence between Timebase Timer Interrupt and EI2OS .......................................... 187 Correspondence to EI2OS Function ................... 228 EI2OS Function of 16-bit Reload Timer ............. 251 EI2OS Function of 8-/10-bit A/D Converter........ 358 EI2OS Operation Flow........................................ 79 Extended Intelligent I/O Service (EI2OS) .......
INDEX Sector Configuration of the 512K-bit Flash Memory .......................................................... 531 Setting the Flash Memory to the Read/reset State .......................................................... 545 Writing Data to the Flash Memory ..................... 546 Writing to the Flash Memory............................. 546 Writing to/erasing Flash Memory....................... 530 Flash Memory Control Status Register Flash Memory Control Status Register (FMCS) .....................
INDEX Precautions for Use of "DIV A,Ri" and "DIVW A,RWi" Instructions.................. 52 Restrictions on Interrupt Disable Instructions and Prefix Instructions........................... 51 Use of the "DIV A,Ri" and "DIVW A,RWi" Instructions without Precautions ............ 53 Instruction List F2MC-16LX Instruction List ............................. 600 Instruction Map Structure of Instruction Map .............................
INDEX LIN-master-slave Communication LIN-master-slave Communication Function........ 438 LIN-UART Block Diagram of LIN-UART ........................... 387 Block Diagram of LIN-UART Pins.................... 391 LIN-UART as LIN Master Device ..................... 439 LIN-UART Baud Rate Selection........................ 413 LIN-UART Direct Pin Access ........................... 432 LIN-UART Functions....................................... 382 LIN-UART Interrupts .......................................
INDEX Message Buffer Control Registers Message Buffer Control Registers ..................... 452 Microcontroller Connection of an Oscillator or an External Clock to the Microcontroller.......................... 108 Minimum Connection Example of Minimum Connection to Flash Microcomputer Programmer ................ 563 Example of Minimum Connection to Flash microcontroller Programmer ................ 561 Mode Data Mode Data ......................................................
INDEX Patch Processing Flow of Patch Processing for Patch Program....... 520 Patch Program Flow of Patch Processing for Patch Program....... 520 Pause-conversion Mode Operation of Pause-conversion Mode ................. 365 Pause-conversion Mode (ADCS:MD1,MD0= "11B" ) ................ 359 Setting of Pause-conversion Mode ..................... 364 PC Program Counter (PC) ........................................ 45 PDR Port Data Register (PDR) ..................................
INDEX PSCCR Configuration of the PLL/Subclock Control Register (PSCCR) ............................................ 101 PUCR Block Diagram of Pull-up Control Register (PUCR) .......................................................... 174 Pull-up Control Register (PUCR) ...................... 174 Pull-up Control Register Block Diagram of Pull-up Control Register (PUCR) .......................................................... 174 Pull-up Control Register (PUCR) ...................... 174 R RAM RAM area .....
INDEX List of Registers and Reset Values of ROM Mirroring Function Select Module ....................... 527 ROM Mirroring Function Select Register ROM Mirroring Function Select Register (ROMM) .......................................................... 528 ROMM ROM Mirroring Function Select Register (ROMM) .......................................................... 528 ROM Security Function Overview of ROM Security Function ................. 566 RP Register Bank Pointer (RP) .................................
INDEX Sub-clock Oscillation Stabilization Wait Time Timer of Subclock ............................................ 277 Sub-clock Mode............................................... 116 Sub-clock Mode Transition Operating When Sub-clock Has Already Stopped ........... 116 Sub-clock Mode with External Single Clock Product .......................................................... 116 Symbols Description of Instruction Presentation Items and symbols..............................................
INDEX LIN-UART as LIN Master Device ..................... 439 LIN-UART Baud Rate Selection........................ 413 LIN-UART Direct Pin Access ........................... 432 LIN-UART Functions....................................... 382 LIN-UART Interrupts ....................................... 406 LIN-UART Interrupts and EI2OS....................... 408 LIN-UART Pins............................................... 391 LIN-UART Registers........................................
CM44-10136-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MCTM-16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL April 2005 the first edition Published FUJITSU LIMITED Edited Business Promotion Dept.
