FUJITSU MICROELECTRONICS CONTROLLER MANUAL CM71-00105-1E FR81 Family 32-BIT MICROCONTROLLER PROGRAMMING MANUAL
FR81 Family 32-BIT MICROCONTROLLER PROGRAMMING MANUAL For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.
PREFACE ■ Objectives and targeted reader FR81 Family is a 32 bit single chip microcontroller with CPU of new RISC Architecture as the core. FR81 Family has specifications that are optimum for embedded use requiring high performance CPU processing power. This manual explains the programming model and execution instructions for engineers developing a product using this FR81 Family Microcontroller, especially the programmers who produce programs using assembly language of the assembler for FR/FR80/FR81 Family.
• • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information.
CONTENTS CHAPTER 1 1.1 1.2 OVERVIEW OF FR81 FAMILY CPU ............................................................ 1 Features of FR81 Family CPU ............................................................................................................ 2 Changes from the earlier FR Family ................................................................................................... 4 CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 7 2.
CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 41 4.1 Reset ................................................................................................................................................ 4.2 Basic Operations in EIT Processing ................................................................................................. 4.2.1 Types of EIT Processing and Prior Preparation .................................................................
5.3.1 Occurrence of data hazard .......................................................................................................... 5.3.2 Register Bypassing ...................................................................................................................... 5.3.3 Interlocking .................................................................................................................................. 5.3.
7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 7.43 7.44 7.45 7.46 7.47 7.48 7.49 7.50 7.51 7.52 7.53 7.54 7.55 7.56 7.57 7.58 7.59 7.60 vi ASR (Arithmetic shift to the Right Direction) ................................................................................... ASR2 (Arithmetic shift to the Right Direction) .................................................................................
7.61 7.62 7.63 7.64 7.65 7.66 7.67 7.68 7.69 7.70 7.71 7.72 7.73 7.74 7.75 7.76 7.77 7.78 7.79 7.80 7.81 7.82 7.83 7.84 7.85 7.86 7.87 7.88 7.89 7.90 7.91 7.92 7.93 7.94 7.95 7.96 7.97 7.98 7.99 7.100 7.101 7.102 7.103 7.104 7.105 7.106 7.107 EXTUB (Unsign Extend from Byte Data to Word Data) .................................................................. EXTUH (Unsign Extend from Byte Data to Word Data) ..................................................................
7.108 7.109 7.110 7.111 7.112 7.113 7.114 7.115 7.116 7.117 7.118 7.119 7.120 7.121 7.122 7.123 7.124 7.125 7.126 7.127 7.128 7.129 7.130 7.131 7.132 7.133 7.134 7.135 7.136 7.137 7.138 7.139 7.140 7.141 7.142 7.143 7.144 7.145 7.146 7.147 7.148 7.149 7.150 7.151 7.152 7.153 7.154 viii LDI:8 (Load Immediate 8bit Data to Destination Register) ............................................................. LDM0 (Load Multiple Registers) .........................................................................
7.155 7.156 7.157 7.158 7.159 7.160 7.161 7.162 7.163 7.164 7.165 7.166 7.167 7.168 7.169 7.170 7.171 ST (Store Word Data in Register to Memory) ................................................................................. ST (Store Word Data in Program Status Register to Memory) ....................................................... STB (Store Byte Data in Register to Memory) ................................................................................ STB (Store Byte Data in Register to Memory) .
x
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU This chapter describes the features of FR81 Family CPU and the changes from the earlier FR Family. 1.1 Features of FR81 Family CPU 1.
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.1 1.1 FR81 Family Features of FR81 Family CPU FR81 Family CPU is meant for 32 bit RISC controller having proprietary FR81 architecture of Fujitsu. The FR81 architecture is optimized for microcontrollers by using the FR family instruction set and including improved floating-point, memory protection, and debug functions. ■ General-purpose Register Architecture It is load/store architecture based on 16 numbers of 32-bit General-purpose registers R0 to R15.
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.1 FR81 Family ■ Harvard Architecture An instruction can be executed efficiently based on Harvard Architecture where instruction bus for instruction access and data bus for data access are independent. ■ Multiplication Instruction Multiplication/division computation can be executed at the instruction level based on an in-built multiplier. 32-bit multiplication, signed or unsigned, is executed in 5 cycles. 16-bit multiplication is executed in 3 cycles.
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.2 1.2 FR81 Family Changes from the earlier FR Family FR81 Family has partial addition and deletion of instructions and operational changes from the earlier FR Family (FR30 Family, FR60 Family etc.). ■ Instructions that cannot be used in FR81/FR80 Family Following instructions cannot be used in FR81/FR80 Family.
FR81 Family CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.2 ■ Operation of INTE Instructions during Step Execution In FR81 Family, trap processing is initiated based on INTE instructions even during step execution based on step trace trap. In hitherto FR Family, trap processing is not initiated based on INTE instructions during step execution. For trap processing based on step trace trap and INTE instructions, see “4.6 Traps”.
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU 1.
CHAPTER 2 MEMORY ARCHITECTURE This chapter explains the memory architecture of FR81 Family CPU. Memory architecture refers to allocation of memory spaces and methods used to access memory. 2.1 Address Space 2.2 Data Structure 2.
CHAPTER 2 MEMORY ARCHITECTURE 2.1 2.1 FR81 Family Address Space The address space of FR81 Family CPU is 32 bits (4Gbyte). CPU controls the address spaces in byte units. An address on the address space is accessed from the CPU by specifying a 32-bit value. Address space is indicated in Figure 2.1-1. Figure 2.
CHAPTER 2 MEMORY ARCHITECTURE 2.1 FR81 Family • byte data access: Lower 8 bits of the address are used as it is • half word data access: Value is doubled and used as lower 9 bits of the address • word data access: Value is quadrupled and used as lower 10 bits of the address The relation between data types specified by direct address and memory address is shown in Figure 2.1-2. Figure 2.
CHAPTER 2 MEMORY ARCHITECTURE 2.1 FR81 Family As a result of reset, the value of Table Base Register (TBR) is initialized to 000F FC00H, and the range of vector table area extends from 000F FC00H to 000F FFFFH. By rewriting the Table Base Register (TBR), the vector table area can be allocated to any desired location. A vector table is composed of entry addresses for each EIT processing programs.
CHAPTER 2 MEMORY ARCHITECTURE 2.1 FR81 Family 2.1.3 20-bit Addressing Area & 32-bit Addressing Area The lower portion of the address space extending from 0000 0000H to 000F FFFFH (1Mbyte) will be the 20-bit addressing area. The overall address space from 0000 0000H to FFFF FFFFH will be 32-bit addressing space. If all the program locations and data locations are positioned within the 20-bit addressing area, a compact and high-speed program can be realized as compared to a 32-bit addressing area.
CHAPTER 2 MEMORY ARCHITECTURE 2.2 2.2 FR81 Family Data Structure FR81 Family CPU has three data types namely byte data (8-bits), half word data (16-bits) and word data (32-bits). The byte order is big endian. 2.2.1 Byte Data This is a data type having 8 bits as unit. Bit order is little endian, MSB side becomes bit7 and LSB side becomes bit0. The structure of byte data is shown in Figure 2.2-1. Figure 2.2-1 Structure of byte data MSB bit 2.2.
CHAPTER 2 MEMORY ARCHITECTURE 2.2 FR81 Family 2.2.4 Byte Order The byte order of FR81 Family CPU is big endian. When word data or half word data are allocated to address spaces, the higher bytes are placed in the lower address side while the lower bytes are placed in the higher address side. The arrangement of big endian byte data is shown in Figure 2.2-4.
CHAPTER 2 MEMORY ARCHITECTURE 2.3 2.3 FR81 Family Word Alignment The data type used determines restrictions on the designation of memory addresses (word alignment). 2.3.1 Program Access Unit of instruction length is half word (2byte) and all instructions are allocated to addresses which are multiples of 2 (2n location). At the time of execution of the instruction, bit0 of the program counter (PC) automatically becomes "0", and is always at an even address.
CHAPTER 3 PROGRAMMING MODEL This chapter describes the programming model of FR81 Family CPU. 3.1 Register Configuration 3.2 General-purpose Registers 3.3 Dedicated Registers 3.
CHAPTER 3 PROGRAMMING MODEL 3.1 3.1 FR81 Family Register Configuration FR81 Family CPU uses three types of registers, namely, general-purpose registers, dedicated registers and floating point registers. General-purpose registers are registers that store computation data and address information. They comprise 16 registers from R0 to R15. Dedicated registers are registers that store information for specific applications.
CHAPTER 3 PROGRAMMING MODEL 3.2 FR81 Family 3.2 General-purpose Registers General-purpose registers are used for storing results of various calculations, as well as information about addresses to be used as pointers for memory access. 3.2.1 Configuration of General-purpose Registers General-purpose registers has sixteen each 32 bits in length. General-purpose registers have names R0 to R15. In case of general instructions, the general-purpose registers can use without any distinction.
CHAPTER 3 PROGRAMMING MODEL 3.2 3.2.2 FR81 Family Special Usage of General-purpose Registers General-purpose registers R13 to R15, besides being used as other general-purpose registers, are used in the following way in some instructions.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family 3.3 Dedicated Registers FR81 Family CPU has dedicated registers reserved for special usages. 3.3.1 Configuration of Dedicated Registers Dedicated registers are used for special purposes. The following dedicated registers are available.
CHAPTER 3 PROGRAMMING MODEL 3.3 3.3.2 FR81 Family Program Counter (PC) Program counter (PC) is a 32-bit register that indicates the address containing the instruction that is currently executing. Figure 3.3-2 shows the bit configuration of program counter (PC). Figure 3.3-2 Program Counter (PC) Bit Configuration bit0 bit31 Initial value XXXX XXXX H The value of the lowest bit (LBS) of the program counter (PC) is always read as “0”.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family 3.3.4 System Status Register (SSR) System status register (SSR) is a 4-bit register that indicates the state of the CPU. It lies between bit 31 and bit 28 of the program status (PS). Figure 3.3-4 shows the bit configuration of system status register (SSR). Figure 3.3-4 System Status Register (SSR) Bit Configuration bit31 DBG bit30 bit29 bit28 UM FPU MPU Initial value 0011B The contents of each bit are described below.
CHAPTER 3 PROGRAMMING MODEL 3.3 3.3.5 FR81 Family Interrupt Level Mask Register (ILM) Interrupt level mask register (ILM) is a 5-bit register used to store the interrupt level mask value. It lies between bit20 to bit16 of the program status (PS). Figure 3.3-5 shows the bit configuration of interrupt level mask register (ILM). Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family 3.3.6 Condition Code Register (CCR) Condition code register (CCR) is an 8-bit register that indicates the status of instruction execution. It lies between bit7 to bit0 of the program status (PS). Figure 3.3-7 shows the bit configuration of condition code register (CCR). Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family [bit3] N: Negative Flag This flag is used to indicate positive or negative values when the results of a calculation are expressed in two’s complement form. The value "0" of the negative flag (N) indicates a positive value while "1" indicates a negative value. Table 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family 3.3.7 System Condition Code Register (SCR) System condition code register (SCR) is a 3-bit register used to control the intermediate data of stepwise division and step trace trap. It lies between bit10 to bit8 of the program status (PS). Figure 3.3-8 shows the bit configuration of system condition code register (SCR). Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 3.3.8 FR81 Family Return Pointer (RP) Return pointer (RP) is a 32-bit register which stores the address for returning from a subroutine. It stores the program counter (PC) value upon execution of a CALL instruction. Figure 3.3-9 shows the bit configuration of return pointer (RP). Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family Figure 3.3-11 Sample Operation of RP during Execution of a RET Instruction. Memory space Before execution Memory space After execution CALL SUB1 PC SUB1 RP 1234567AH ADD #1,R0 SUB1 3.3.9 CALL SUB1 PC 1234567AH RP 1234567AH RET ADD #1,R0 SUB1 RET System Stack Pointer (SSP) The system stack pointer (SSP) is a 32-bit register that indicates the address to be saved/restored to the system stack used at the time of EIT processing.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family Figure 3.3-13 Example of System Stack Pointer (SSP) Operation Before execution of ST R13,@-R15 After execution of ST R13,@-R15 Memory space 00000000H SSP 12345678H USP 76543210H R13 17263540H S CCR 3.3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family Figure 3.3-15 Example of User Stack Pointer (USP) Operation Before execution of ST R13,@-R15 After execution of ST R13,@-R15 Memory space 00000000H SSP 12345678H USP 76543210H R13 17263540H S CCR 3.3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family The reset value of table base register (TBR) is 000F FC00H. Do not set a value above FFFF FC00H for the table base register (TBR). Precautions: If values greater than FFFF FC00H are assigned to the table base register (TBR), this operation may result in an overflow when summed with the offset value. An overflow in turn will result in vector access to the area 0000 0000H to 0000 03FFH, which can cause a program run away. 3.3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family Figure 3.3-19 Example of Multiplication Operation using Multiplication/Division Register (MDH, MDL) Before execution of instruction MUL R0,R1 After execution of instruction MUL R0,R1 R0 12345678H R0 12345678H R1 76543210H R1 76543210H MDH, MDL ???????? ???????? H MDH, MDL 086A1C97 0B88D780 H ● Function during Division Before starting the calculation, the dividend is stored in the Multiplication/Division register (MDH, MDL).
CHAPTER 3 PROGRAMMING MODEL 3.3 3.3.13 FR81 Family Base Pointer (BP) The base pointer (BP) register is used for pointing in base pointer indirect addressing mode. Figure 3.3-21 shows the bit configuration of base pointer (BP). Figure 3.3-21 Base Pointer (BP) Bit Configuration bit0 bit31 Initial value XXXX XXXX H 3.3.14 FPU Control Register (FCR) FPU control register (FCR) is a 32-bit register used to control the FPU. It has a flag that indicates the settings and status of the FPU operation mode.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family The content of each bit are described below. [bit31] E : E flag This flag indicates that FRj and FRi are equal based on the floating point compare instruction (FCMP) results. [bit30] L : L flag This flag indicates that FRi is less than FRj based on the floating point compare instruction (FCMP) results. [bit29] G : G flag This flag indicates that FRi is greater than FRj based on the floating point compare instruction (FCMP) results.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family ■ Floating point exception enable flag (EEF) Floating point exception enable flag (EEF) is a 6-bit register that enables exception occurrences of floating point calculation. It lies between bit 17 and bit 12 of the FPU control register (FCR). Figure 3.3-25 shows the bit configuration of the floating point exception enable flag (EEF). Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family ■ Floating point exception accumulative flag (ECF) Floating point exception accumulative flag (ECF) is a 6-bit register that indicates the accumulative number of occurrences of floating point calculation exceptions. It lies between bit 11 and bit 6 of the FPU control register (FCR). Only a "0" can be written in the accumulative flags. The flag value will not be changed when "1" is written in the accumulative flags. The write value is evaluated by bit. Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family ■ Floating point exception flag (CFE) Floating point exception flag (CFE) is a 6-bit register that indicates the exception occurrence of floating point calculation. It lies between bit 5 and bit 0 of the FPU control register (FCR). Each flag is set according to the calculation result. Each flag shall be cleared using software. Each flag can be set only to "0", and writing "1" to the flag is invalid. The write value is evaluated by bit.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family 3.3.15 Exception status register (ESR) This is a 32-bit register that indicates the balance of process when an exception occurs while executing the invalid instruction exception source and the multiple load/store instruction. The exception status register (ESR) consists of the following two parts: • Register list (RL) • Invalid instruction exception source (INV) Figure 3.3-28 shows the bit configuration of the exception status register (ESR). Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family ■ Invalid instruction exception source (INV) Invalid instruction exception source (INV) is a 7-bit register that indicates the source causing an invalid instruction exception. It lies between bit 6 and bit 0 of the exception status register (ESR). Each flag is set only when the source occurs. Each flag shall be cleared using software. Each flag can be set only to "0", and writing "1" to the flag is invalid. The write value is evaluated by bit. Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.3 FR81 Family 3.3.16 Debug Register (DBR) The debug register (DBR) is a dedicated register accessible only in the debug state. Writing to this register other than in debug state is regarded as invalid. Figure 3.3-31 shows the bit configuration of Debug Register (DBR). Figure 3.
CHAPTER 3 PROGRAMMING MODEL 3.4 3.4 FR81 Family Floating-point Register Floating point registers are using that store results for floating point calculations. The floating-point register is 16, each having 32-bit length. As for the register, the name of FR0 to FR15 is named. Figure 3.4-1 shows the construction and the initial value of the floating-point register. Figure 3.
CHAPTER 4 RESET AND "EIT" PROCESSING This chapter describes reset and EIT processing in the FR81 family CPU. EIT processing is the generic name for exceptions, interrupt and trap. 4.1 Reset 4.2 Basic Operations in EIT Processing 4.3 Processor Operation Status 4.4 Exception Processing 4.5 Interrupts 4.6 Traps 4.7 Multiple EIT processing and Priority Levels 4.8 Timing When Register Settings Are Reflected 4.9 Usage Sequence of General Interrupts 4.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.1 4.1 FR81 Family Reset A reset forcibly terminates the current process, initializes the device, and restarts the program from the reset vector entry address. The reset process is executed in privilege mode. Transition to user mode should be carried out by executing a RETI instruction. When a reset is generated, CPU terminates the processing of the instruction execution at that time and goes into inactive status until the reset is cancelled.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.2 FR81 Family 4.2 Basic Operations in EIT Processing Exceptions, interrupts and traps are similar operations applied under partially different conditions. They save information for terminating or restarting the execution of instructions and perform branching to a processing program. 4.2.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.2 4.2.2 FR81 Family EIT Processing Sequence FR81 family CPU processes EIT events as follows. 1. The vector table indicated by the table base register (TBR) and the offset value of the vector number corresponding to the particular EIT are used to determine the entry address for the processing program for the EIT. 2.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.2 FR81 Family Figure 4.2-2 Example of storing of PC, PS during an EIT event occurrence [Example] SSP [Before interrupt] [After interrupt] SSP 80000000 H Memory Memory 7FFFFFF8 H 7FFFFFFC H 80000000 H 4.2.3 7FFFFFF8 H 7FFFFFF8 H 7FFFFFFC H 80000000 H PC PS Recovery from EIT Processing RETI instruction is used for recovery from an EIT processing program.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.3 4.3 FR81 Family Processor Operation Status Processor operation is comprised of four states: Reset, normal operation, low-power consumption, and debugging. ● Reset state A state where the CPU is being reset. Two levels are provided for the reset state: Initialize level and reset level. When an initialize level reset is issued, all functions inside the MCU chip are initialized.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.3 FR81 Family Figure 4.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4 4.4 FR81 Family Exception Processing Exceptions originate when there is a problem in the instruction sequence. Exceptions are processed by first saving the necessary information to resume the currently executing instruction, and then starting the processing routine corresponding to the type of exception that has occurred. Branching to the exception processing routine takes place before execution of the instruction that has caused the exception.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4 FR81 Family 4. The program counter (PC) value is updated by referring to the vector table. (TBR + 3C4H) → PC 5. A new EIT event is detected. The address saved to the system stack as a program counter (PC) value represents the instruction itself that caused the undefined instruction exception.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4 FR81 Family If this exception occurs while executing LDM0, LDM1, STM0, STM1, FLDM, or FSTM instruction, contents of execution until the occurrence are reflected in registers and memory. Check the register list (ESR:RL) for how far the instruction is executed. Upon acceptance of the instruction access protection violation exception, the following operations take place. 1. Transition to privilege mode is carried out, and the stack flag (S) is cleared.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4 FR81 Family 3. The contents of the program counter (PC) of an exception source instruction are saved to the system stack. SSP - 4 → SSP PC → (SSP) 4. The program counter (PC) value is updated by referring to the vector table. (TBR + 3E8H) → PC 5. A new EIT event is detected. 4.4.5 Instruction Break An instruction break generates an exception or a break based on address instructions given by the debug support unit (DSU).
CHAPTER 4 RESET AND "EIT" PROCESSING 4.4 4.4.6 FR81 Family Guarded Access Break Guarded access break is a function that carries out a break processing instead of generating an exception when an instruction access protection violation or a data access protection violation occurs during debugging. Whether each access protection violation is treated as a break or an exception processing is determined by the debugger. The guarded access break does not occur during normal operation.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5 FR81 Family 4.5 Interrupts Interrupts originate independently of the instruction sequence. They are processed by saving the necessary information to resume the currently executing instruction sequence, and then starting the processing routine corresponding to the type of the interrupt that has occurred interrupt. Instruction loaded and executing in the CPU before the interrupt will be executed till completion.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5 FR81 Family Figure 4.5-1 Acceptance Procedure of General Interrupts FR81 family CPU PS INT request I SSP USP ILM Interrupt controller Peripheral device ICR#n Interrupt enable bit S compare AND Each interrupt request is assigned an interrupt level by the interrupt controller, and it is possible to mask requests according to their level values.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5 FR81 Family 4.5.2 Non-maskable Interrupts (NMI) Non-maskable interrupts (NMI) are interrupts that cannot be masked. Depending upon the product series, there are models which do not support NMI (there are no external NMI terminals). Refer to the hardware manual of various models to check whether NMI is supported or not.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.5 FR81 Family 3. The contents of the program status (PS) are saved to the PS save register (PSSR). PS → PSSR 4. The contents of the program counter (PC) of the instruction next to that accepted the break interrupt are saved to the PC save register (PCSR). PC → PCSR 5. An instruction is fetched from the emulator debug instruction register (EIDR1), and the handler is executed. 4.5.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.6 FR81 Family 4.6 Traps Traps are generated from within the instruction sequence. Traps are processed by first saving the necessary information to resume processing from the next instruction in the sequence, and then starting the processing routine corresponding to the type of the trap that has occurred. Branching to the processing routine takes place after execution of the instruction that has caused the trap.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.6 FR81 Family The following operations are carried out when an INTE instruction is executed during normal operation. 1. Transition to privilege mode is carried out, the stack flag (S) is cleared, and 4 is set to the interrupt level mask register (ILM). "0" → UM "0" → S "4" → ILM 2. The contents of the program status (PS) are saved to the system stack. SSP - 4 → SSP PS → (SSP) 3.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.6 FR81 Family A step trace trap is generated when the following conditions are met. • Step trace trap flag (T) in the system condition code register (SCR) is set to "1". • The currently executing instruction is not a delayed branching instruction • User state in which CPU is in normal operation or debugging Step trace trap is not generated immediately after the execution of a delayed branching instruction.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.7 4.7 FR81 Family Multiple EIT processing and Priority Levels When multiple EIT requests occur at the same time, priority levels are used to select one source and execute the corresponding EIT sequence. 4.7.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.7 FR81 Family 4.7.2 Priority Levels of EIT Requests The sequence of accepting each request and executing the corresponding processing routines when multiple EIT request occur simultaneously, is decided by two factors - by the priority levels of EIT requests, and, how other EIT requests are to be masked when one EIT request has been accepted.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.7 FR81 Family EIT Acceptance when Branching Instruction is Executed 4.7.3 No interrupts are accepted when a branching instruction is executed for delayed branching instruction. Also, when an exception occurs in the delay slot, branching is cancelled, and the program counter (PC) for branching instruction is saved. Interrupts and traps are accepted for delay slot instruction. Table 4.7-2 shows the EIT acceptance and saved PC value for branching instructions. Table 4.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.8 FR81 Family 4.8 Timing When Register Settings Are Reflected The timing when the new values are reflected after the interrupt enable flag (I) of program status (PS) and the value of interrupt level mask register (ILM) are modified will be explained in this section. 4.8.1 Timing when the interrupt enable flag (I) is requested The interrupt request (enable/disable) is reflected from the instruction which modifies the value of interrupt enable flag (I). Figure 4.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.8 4.8.2 FR81 Family Timing of Reflection of Interrupt Level Mask Register (ILM) Acceptance to interrupt request is reflected from the instruction which modifies the value of interrupt level mask register (ILM). Figure 4.8-3 shows the timing of reflection when the interrupt level mask register (ILM) is modified. Figure 4.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.9 FR81 Family 4.9 Usage Sequence of General Interrupts General interrupts accept interrupt requests from in-built peripheral functions and external terminals, and perform EIT processing. The general points of caution of programming while using general interrupts have been described here. Refer to the hardware manual of various models as the detailed procedure differs as per the peripheral function. 4.9.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.9 4.9.2 FR81 Family Processing during an Interrupt Processing Routine After the interrupt request for a general interrupt has been accepted in the CPU as EIT following its generation, the control moves to the interrupt processing routine after the execution of the EIT sequence. Vector numbers are assigned to each source of general interrupts, and the interrupt processing routine corresponding to these vector numbers are started.
FR81 Family 4.10 CHAPTER 4 RESET AND "EIT" PROCESSING 4.10 Precautions The precautions of The reset and the EIT processing described here. 4.10.1 Exceptions in EIT Sequence and RETI Sequence If a data access protection violation exception (including guarded access break) or invalid instruction exception (data access error) occurs in the EIT or RETI sequence, since access to the system stack area is disabled, the CPU goes into the inactive state.
CHAPTER 4 RESET AND "EIT" PROCESSING 4.
CHAPTER 5 PIPELINE OPERATION This chapter explains the chief characteristics of FR81 family CPU like pipeline operation, delayed branching processing etc. 5.1 Instruction execution based on Pipeline 5.2 Pipeline Operation and Interrupt Processing 5.3 Pipeline hazards 5.4 Non-block loading 5.
CHAPTER 5 PIPELINE OPERATION 5.1 5.1 FR81 Family Instruction execution based on Pipeline FR81 Family CPU processes a instruction using a pipeline operation. This makes it possible to process to process nearly all instructions in one cycle. FR81 Family has two pipelines: an integer pipeline and floating point pipeline.
CHAPTER 5 PIPELINE OPERATION 5.1 FR81 Family Figure 5.1-1 Example of integer pipeline operation (1) (Example 1) LD @R10, R1 LDI:8 #0x02, R2 CMP R1, R2 IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA BNE:D Label_G ADD #0x1, R1 WB In principle, execution of instructions is carried out at one instruction per cycle.
CHAPTER 5 PIPELINE OPERATION 5.1 5.1.2 FR81 Family Floating Point Pipeline The floating point pipeline is a 6-stage pipeline used to execute floating point calculations. The IF stage and ID stage are common with the integer pipeline. The floating point pipeline has the following 5-stage configuration. • IF Stage: Fetch Instruction Instruction address is generated and instruction is fetched. • ID Stage: Decode Instruction Fetched instruction is decoded. Register reading is also carried out.
CHAPTER 5 PIPELINE OPERATION 5.2 FR81 Family 5.2 Pipeline Operation and Interrupt Processing It is possible at times that an event wherein it appears that interrupt request is lost after acceptance of interrupt, if the flag that causes interrupt in the interrupt-enabled condition, because pipeline operation is conducted, occurs. 5.2.
CHAPTER 5 PIPELINE OPERATION 5.3 5.3 FR81 Family Pipeline hazards The FR81 Family CPU executes program steps in the order in which they are written and is therefore equipped with a function that detects the occurrence of data hazards and construction hazards, and stops pipeline processing when necessary. 5.3.1 Occurrence of data hazard A data hazard occurs if dependency that refers or updates the register exists in between the preceding and subsequent instructions.
CHAPTER 5 PIPELINE OPERATION 5.3 FR81 Family 5.3.3 Interlocking Instructions that are relatively slow in loading data to the CPU may cause data hazards that cannot be handled by register bypassing. In the example Figure 5.3-3, data required for the ID stage of the SUB instruction must be loaded to the CPU in the MA stage of the LD instruction, creating a data hazard that cannot be avoided by the bypass function. Figure 5.
CHAPTER 5 PIPELINE OPERATION 5.3 5.3.6 FR81 Family Control Hazard A control hazard occurs when the next instruction cannot be fetched before the branching instruction is complete. In FR81 Family, to reduce penalty due to this control hazard, the pre-fetch function that bypasses the branch destination address from the ID stage and the delayed branching instruction have been added. Therefore, penalties do not become apparent.
CHAPTER 5 PIPELINE OPERATION 5.4 FR81 Family 5.4 Non-block loading Non-block loading is carried out in FR81 Family CPU. A maximum of 4 loading instructions can be issued with precedence. In non-block loading, the subsequent instruction is executed without waiting for the completion of loading instruction, if the general-purpose register in which the load instruction value is stored is not referred in the subsequent instruction.
CHAPTER 5 PIPELINE OPERATION 5.5 5.5 FR81 Family Delayed branching processing Because FR81 Family CPU features pipeline operation, the loading of the instruction is already completed at the time of execution of branching instruction. The processing speeds can be improved by using the delayed branching processing. 5.5.
CHAPTER 5 PIPELINE OPERATION 5.5 FR81 Family Figure 5.5-2 Example of processing of Non-Delayed Branching instruction (Branching conditions not satisfied) LD @R10, R1 IF LD @R11, R2 ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB IF ID EX MA WB Not canceled IF ID EX MA WB ADD R1, R3 ST R2, @R12(instruction immediately after) ADD #4, R12(subsequent instruction) 5.5.
CHAPTER 5 PIPELINE OPERATION 5.5 FR81 Family Figure 5.5-4 shows an example of processing a delayed branching instruction when branching conditions are not satisfied. In this example, the instruction "ST R2,@R12" in delay slot is executed without being cancelled. As a result, the program is processed in the order in which it is written. The branching instruction requires an apparent processing time of 1 cycle. Figure 5.
CHAPTER 6 INSTRUCTION OVERVIEW This chapter presents an overview of the instructions used with the FR81 Family CPU. 6.1 Instruction System 6.2 Instructions Formats 6.3 Data Format 6.4 Read-Modify-Write type Instructions 6.5 Branching Instructions and Delay Slot 6.
CHAPTER 6 INSTRUCTION OVERVIEW 6.1 6.1 FR81 Family Instruction System FR81 Family CPU has the integer type instruction of upward compatibility with FR80 Family and floating point type instruction executed by FPU. 6.1.1 Integer Type Instructions Integer type instructions, in addition to instruction type of general RISC CPU, is also compatible with logical operation optimized for embedded use, bit operation and direct addressing instructions.
CHAPTER 6 INSTRUCTION OVERVIEW 6.1 FR81 Family ● Immediate Data Transfer Instructions These are the instructions to transfer immediate data to general-purpose registers and can transfer immediate data of 8bit, 20 bit, and 32 bit. ● Memory Load Instructions These are the instructions to load from memory (including I/O) to general-purpose registers or dedicated registers. They can transfer data length of 3 types namely, bytes, half-words and words and memory addressing is register indirect.
CHAPTER 6 INSTRUCTION OVERVIEW 6.1 FR81 Family ● Bit Search Instructions These are the instructions that have been added to FR81/FR80 Family CPU. They search 32-bit data of general-purpose register from MSB and obtain the first "1" bit, "0" bit and bit position of change point (distance of bit from MSB). They correspond to bit search module packaged in the family prior to FR81/FR80 Family (FR30 Family, FR60 Family etc.) as peripheral function.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 FR81 Family 6.2 Instructions Formats This part describes about Instruction Formats of FR81 Family CPU. 6.2.1 Instructions Notation Formats ● Integer type instruction The integer type instruction is 2 operand format. There are 3 types of Instruction notation formats depending on the number of operands. Instruction notation formats are as follows.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 6.2.2 FR81 Family Addressing Formats There are several methods for address specification when accessing memory in the memory space or I/O register. Addressing format varies depending on Instruction. @General-purpose Registers It is Register Indirect Addressing. Address indicated by the content of the general-purpose register is accessed.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 FR81 Family 6.2.3 Instruction Formats FR81 Family CPU Instructions are 16-bit in length. Bit configuration of Instructions varies depending on configuration of operands of Instructions. Bit configuration of Instructions classified into groups is called Instruction Formats. There are 14 types of Instructions Formats TYPE-A through TYPE-N.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 FR81 Family TYPE-E It has 12-bit OP Codes (OP) and register designated fields (Ri/Rs). MSB LSB OP Ri/Rs TYPE-E’ It is deformation of TYPE-E. It has 12-bit OP Code (OP). TYPE-E register designated field is fixed to 0000B. It is applied for instructions where 16-bit instruction code such as NOP Instruction or RET Instructions etc. is defined. MSB LSB OP 0 0 0 0 TYPE-F It has 5-bit OP Code (OP) and 11-bit address designated filed (rel11).
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 FR81 Family TYPE-H It has 12bit OP code (OP) and 32bit immediate data field (i32), register designated field (Ri). It has 48-bit length and is applied only for LDI:32 Instruction. MSB (n+0) LSB OP Ri (n+2) i32 (Upper} (n+4) i32 (Lower) TYPE-I It has 12-bit OP Code (OP) and 20-bit address designated filed (rel20). These are the instruction formats that have been added to FR81 Family CPU.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 FR81 Family TYPE-K It has 12-bit OP Code (OP), register designated field (Rj) and floating point register designated filed (FRi). These are the instruction formats that have been added to FR81 Family CPU. MSB LSB (n+0) OP Rj (n+2) - FRi TYPE-L It has 14-bit OP Code (OP) and 14-bit immediate data fields (o14/u14), floating point register designated field (FRi). Immediate data fields are not used in some instructions.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 FR81 Family TYPE-N It has 14-bit OP Code (OP) and floating point register list (frlist). These are the instruction formats that have been added to FR81 Family CPU. MSB LSB (n+0) OP (n+2) 6.2.4 - frlist Register designated Field ● General-purpose register designated Field (Ri/Rj) Among Instruction formats, fields that designate general-purpose register are 4-bit length Ri and Rj.
CHAPTER 6 INSTRUCTION OVERVIEW 6.2 FR81 Family ● Dedicated register designated Field (Rs) Among Instruction formats, field that designates dedicated register is 4-bit length Rs. Relation between bit pattern of dedicated register and register designated field has been indicated in Table 6.2-2. Table 6.
CHAPTER 6 INSTRUCTION OVERVIEW 6.3 FR81 Family 6.3 Data Format This section describes the data type and format supported by FR81 Family CPU. In addition to integer type supported by FR80 and earlier, single precision floating point type has been added. 6.3.1 Data Format Used by Integer Type Instructions (Common with All FR Family) ● Signed integer byte Signed integer byte is represented as consecutive 8 bits.
CHAPTER 6 INSTRUCTION OVERVIEW 6.3 FR81 Family ● Signed integer word Signed integer word is represented as consecutive 32 bits. Bit 31 represents the sign bit (S), and "0" represents positive or zero and "1" represents negative. MSB 31 LSB 0 30 S ● Unsigned integer word Unsigned integer word is represented as consecutive 32 bits. MSB 31 6.3.2 LSB 0 Format Used for Floating Point Type Instructions ● Floating point format The IEEE 754 standard is used for floating point format.
CHAPTER 6 INSTRUCTION OVERVIEW 6.3 FR81 Family ● Single precision floating point (32-bit) This conforms to IEEE754 single precision format and is represented as consecutive 32 bits. In the single precision floating point format, bit 31 represents the sign bit (S), bit 30 to bit 23 represent the exponent bits, and bit 22 to bit 0 represent the fractional bits.
CHAPTER 6 INSTRUCTION OVERVIEW 6.4 6.4 FR81 Family Read-Modify-Write type Instructions Read-Modify-Write type Instructions are those that carry out a series of operations namely, arithmetic processing in the data read from the memory space and write the result in the same address of the memory space.
CHAPTER 6 INSTRUCTION OVERVIEW 6.5 FR81 Family 6.5 Branching Instructions and Delay Slot FR81 Family CPU Branching Instructions are of two types namely, Delayed Branching Instructions and Non-delayed Branching Instructions. 6.5.1 Delayed Branching Instructions In case of Delayed Branching Instructions, prior to execution of Branching Destination Instructions, instructions immediately after Branching Instructions are executed.
CHAPTER 6 INSTRUCTION OVERVIEW 6.5 FR81 Family • Instructions that do not affect the operation even when the order is changed 1 cycle Instructions are those where anyone variable namely 1, a, b, c, d is independently written in the CYC Column of "A.2 Instruction Lists". (Instructions which have 2a or 1+b are not 1 cycle instructions). List of instructions that can be placed in Delay Slot are indicated in "Appendix A.3". EIT processing such as Step Trace Trap, general interrupt, NMI etc.
CHAPTER 6 INSTRUCTION OVERVIEW 6.5 FR81 Family CALL:D Instruction If Return Pointer (RP) is referred to based on Delay Slot Instruction of CALL:D Instruction, updated content will be read based on CALL:D Instruction. [Ex] 6.5.3 CALL:D Label ; Branching after updating of RP MOV RP,R0 ; Execution result of RP of preceding CALL:D Instruction is transferred to R0 Non-Delayed Branching Instructions In case of Non-Delayed Branching Instructions, execution is carried out in the sequence of Instructions.
CHAPTER 6 INSTRUCTION OVERVIEW 6.6 6.6 FR81 Family Step Division Instructions In FR81 Family CPU, 32-bit signed/unsigned division is carried out based on combination of Step Division Instructions. Step Division Instructions are of following types.
CHAPTER 6 INSTRUCTION OVERVIEW 6.6 FR81 Family DIV1 R2 ; #31 DIV1 R2 ; #32 DIV2 R2 DIV3 DIV4S Division results are stored in the following registers. • Multiplication/Division Register (MDL): quotient of signed 32 bit • Multiplication/Division Register (MDH): remainder of signed 32 bit Example of execution of signed division has been indicated in Figure 6.6-1. Figure 6.
CHAPTER 6 INSTRUCTION OVERVIEW 6.6 DIV0S R2 ; divisor in R2 DIV1 R2 ; #1 DIV1 R2 ; #2 DIV1 R2 ; #30 DIV1 R2 ; #31 DIV1 R2 ; #32 FR81 Family ... Division result is stored in the following registers. • Multiplication/Division Register (MDL): quotient of unsigned 32 bit • Multiplication/Division Register (MDH): remainder of unsigned 32 bit Example of execution of unsigned division has been indicated in Figure 6.6-2. Figure 6.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS This chapter explains each of the execution instructions used by the FR81 Family CPU, alphabetically in the reference format.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS FR81 Family Refer to "A.1 Meaning of Symbols" for explanation regarding symbols used in detailed execution instructions. The respective instructions are explained separately in the following items. ● Assembler Format Shows the format of writing the instruction in the assembler language. ● Operation Shows the operation of an instruction by substituting it with an arrow mark (→).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.1 FR81 Family 7.1 ADD (Add 4bit Immediate Data to Destination Register) Adds the result of higher 28 bits of 4-bit immediate data with zero extension(0-15) and stores the results to Ri. ● Assembler Format ADD #i4, Ri ● Operation Ri + extu(i4) → Ri ● Flag Change N C Z C V C C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.2 FR81 Family 7.2 ADD (Add Word Data of Source Register to Destination Register) Adds word data of Rj to Ri, stores result to Ri. ● Assembler Format ADD Rj, Ri ● Operation Ri + Rj → Ri ● Flag Change N C Z C V C C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.3 FR81 Family 7.3 ADD2 (Add 4bit Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with minus extension (-16 to -1) to word data in Ri, stores results to Ri. Unlike SUB instruction, changing C flag of this instruction becomes it as well as the ADD instruction unlike the SUB instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.4 FR81 Family 7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) Adds word data and carry flag (C) of Rj to Ri, stores results in Ri. ● Assembler Format ADDC Rj, Ri ● Operation Ri + Rj + C → Ri ● Flag Change N C Z C V C C C N: Set when MSB of the operation result is "1", cleared when MSB is "0". Z: Set when the operation result is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.5 FR81 Family 7.5 ADDN (Add Immediate Data to Destination Register) Adds the result of the higher 28 bits of the 4-bit immediate data with zero extension (0 to 15) to the word data of Ri, stores the results without changing flag settings. ● Assembler Format ADDN #i4, Ri ● Operation Ri + extu(i4) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.6 FR81 Family 7.6 ADDN (Add Word Data of Source Register to Destination Register) Adds the word data of Rj to the word data of Ri, stores results in Ri without changing flag settings. ● Assembler Format ADDN Rj, Ri ● Operation Ri + Rj → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.7 FR81 Family 7.7 ADDN2 (Add Immediate Data to Destination Register) Adds the result of the higher 28 bits of 4-bit immediate data with minus extension (-16 to -1) to word data in Ri, stores the results in Ri without changing flag settings. ● Assembler Format ADDN2 #i4, Ri ● Operation Ri + extn(i4) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.8 FR81 Family 7.8 ADDSP (Add Stack Pointer and Immediate Data) Adds 4 times the 8-bit immediate data as a signed extended value to the word data of R15 and stores result in R15. Specifies the value of s8 × 14 as s10. ● Assembler Format ADDSP #s10 ● Operation R15 + exts(s8×4) → R15 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.9 FR81 Family 7.9 AND (And Word Data of Source Register to Data in Memory) Takes the logical AND of the word data at memory address Ri and word data in Rj and stores the results to the memory address corresponding to Ri. ● Assembler Format AND Rj,@Ri ● Operation (Ri) & Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.10 FR81 Family 7.10 AND (And Word Data of Source Register to Destination Register) Takes the logical AND of word data in Ri and word data in Rj and stores the results to Rj. ● Assembler Format AND Rj, Ri ● Operation Ri & Rj → Ri ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "“0". Z: Set when the operation result is zero, cleared otherwise. V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.11 FR81 Family 7.11 ANDB (And Byte Data of Source Register to Data in Memory) Takes the logical AND of the byte data at memory address Ri and the byte data in Rj and stores the results at Ri location in the memory. ● Assembler Format ANDB Rj,@Ri ● Operation (Ri) & Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.12 FR81 Family 7.12 ANDCCR (And Condition Code Register and Immediate Data) Takes the logical AND of byte data in the condition code register (CCR) and 8-bit immediate data and returns the results to the CCR. ● Assembler Format ANDCCR #u8 ● Operation User mode: CCR & (u8 | 30H) → CCR Privilege mode CCR & u8 → CCR In user mode, a request to rewrite the stack flag (S) or the interrupt enable flag (I) is ignored.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.12 FR81 Family ● EIT Occurrence and Detection An interrupt is detected (the value of I flag after instruction execution is used).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.13 FR81 Family 7.13 ANDH (And Halfword Data of Source Register to Data in Memory) Takes the logical AND of the half-word data at Ri location of the memory and the halfword data in Rj and stores the results at Ri location of the memory. ● Assembler Format ANDH Rj,@Ri ● Operation (Ri) & Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB (bit15) is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.14 FR81 Family 7.14 ASR (Arithmetic shift to the Right Direction) Makes an arithmetic right shift of the word data in Ri by Rj bits, stores the result to Ri. Only the lower 5 bits of Rj, which designates the size of the shift, are valid and the shift range is 0 to 31 bits. ● Assembler Format ASR Rj, Ri ● Operation Ri >> Rj → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.15 FR81 Family 7.15 ASR (Arithmetic shift to the Right Direction) Makes an arithmetic right shift of the word data in Ri by u4 bits, stores the result to Ri. ● Assembler Format ASR #u4, Ri ● Operation Ri >> u4 → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V: Unchanged. C: Holds the bit value shifted last.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.16 FR81 Family 7.16 ASR2 (Arithmetic shift to the Right Direction) Makes an arithmetic right shift of the word data in Ri by u4+16 bits, stores the result to Ri. ● Assembler Format ASR2 #u4, Ri ● Operation Ri >> {u4 + 16} → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V: Unchanged. C: Holds the bit value shifted last.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.17 FR81 Family 7.17 BANDH (And 4bit Immediate Data to Higher 4bit of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory Ri, stores the results to the memory address corresponding to Ri. ● Assembler Format BANDH #u4,@Ri ● Operation (Ri) & {u4 << 4 + 0F H} → (Ri) [Operation uses higher 4 bits only] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.18 FR81 Family 7.18 BANDL (And 4bit Immediate Data to Lower 4bit of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory Ri, stores the results to the memory address corresponding to Ri. ● Assembler Format BANDL #u4,@Ri ● Operation (Ri) & {F0H + u4} → (Ri) [Operation uses lower 4 bits only] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.19 FR81 Family 7.19 Bcc (Branch relative if Condition satisfied) This is a branching instruction without a delay slot. If the conditions specified for each instruction are satisfied, branch to the address indicated by label9 relative to the value of the program counter (PC). When calculating the address, double the value of rel8 as a signed extension. If conditions are not satisfied, no branching occurs.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.19 FR81 Family ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged. ● Classification Non-delayed branching instruction ● Execution Cycles At time of branching: 2 cycles At the time of no branching: 1 cycle ● Instruction Format MSB 1 LSB 1 1 0 cc rel8 ● Execution Example BHI label ; Bit pattern of the instruction: 1110 1111 0010 1000 ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.20 FR81 Family 7.20 Bcc:D (Branch relative if Condition satisfied) This is a branching instruction with a delay slot. If the conditions established for each particular instruction are satisfied, branch to the address indicated by label9 relative to the value of the program counter (PC). When calculating the address, double the value of rel8 as a signed extension. If conditions are not satisfied, no branching occurs.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.20 FR81 Family ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged. ● Classification Delayed branching instruction ● Execution Cycles 1 cycle ● Instruction Format MSB 1 LSB 1 1 1 cc rel8 ● Execution Example BHI:D label ; Bit pattern of the instruction: 1111 1111 0010 1000 LDI:8 ; Instruction placed in delay slot #255, R1 ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.21 FR81 Family 7.21 BEORH (Eor 4bit Immediate Data to Higher 4bit of Byte Data in Memory) Takes the logical exclusive OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address Ri, stores the results to the memory address corresponding to Ri. ● Assembler Format BEORH #u4,@Ri ● Operation (Ri) ^ {u4 << 4} → (Ri) [Operation uses higher 4 bits only] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.22 FR81 Family 7.22 BEORL (Eor 4bit Immediate Data to Lower 4bit of Byte Data in Memory) Takes the logical exclusive OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address Ri, stores the results to the memory address corresponding to Ri. ● Assembler Format BEORL #u4,@Ri ● Operation (Ri) ^ u4 → (Ri) [Operation uses lower 4 bits only] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.23 FR81 Family 7.23 BORH (Or 4bit Immediate Data to Higher 4bit of Byte Data in Memory) Takes the logical OR of the 4-bit immediate data and the higher 4 bits of byte data at memory address Ri, stores the results to the memory address corresponding to Ri. ● Assembler Format BORH #u4,@Ri ● Operation (Ri) | {u4 << 4} → (Ri) [Operation uses higher 4 bits only] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.24 FR81 Family 7.24 BORL (Or 4bit Immediate Data to Lower 4bit of Byte Data in Memory) Takes the logical OR of the 4-bit immediate data and the lower 4 bits of byte data at memory address Ri, stores the results to the memory address corresponding to Ri. ● Assembler Format BORL #u4,@Ri ● Operation (Ri) | u4 → (Ri) [Operation uses lower 4 bits only] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.25 FR81 Family 7.25 BTSTH (Test Higher 4bit of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at memory address Ri places the results in the condition code register (CCR). ● Assembler Format BTSTH #u4,@Ri ● Operation (Ri) & {u4 << 4} [Test uses higher 4 bits only] ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB(bit7) is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.26 FR81 Family 7.26 BTSTL (Test Lower 4bit of Byte Data in Memory) Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at memory address Ri, places the results in the flag of the condition code register. ● Assembler Format BTSTL #u4,@Ri ● Operation (Ri) & u4 [Test uses lower 4 bits only] ● Flag Change N 0 Z C V - C - N: Cleared. Z: Set when the operation result is zero, cleared otherwise. V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.27 FR81 Family 7.27 CALL (Call Subroutine) This is a branching instruction without a delay slot. After storing the address of the next instruction in the return pointer (RP), branch to the address indicated by label12 relative to the value of the program counter (PC). When calculating the address, double the value of rel11 as a signed extension.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.27 FR81 Family ● Execution Example CALL label ; Bit pattern of the instruction: 1101 0000 1001 0000 ...
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.28 FR81 Family 7.28 CALL (Call Subroutine) This is a branching instruction without a delay slot. After saving the address of the next instruction in the return pointer (RP), a branch to the address indicated by Ri occurs. ● Assembler Format CALL @Ri ● Operation PC + 2 → RP Ri → PC ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.29 FR81 Family 7.29 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the return pointer (RP), branch to the address indicated by label12 relative to the value of the program counter (PC). When calculating the address, double the value of rel11 as a signed extension.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.30 FR81 Family 7.30 CALL:D (Call Subroutine) This is a branching instruction with a delay slot. After saving the address of the next instruction after the delay slot to the return pointer (RP), it branches to the address indicated by Ri. ● Assembler Format CALL:D @Ri ● Operation PC + 4 → RP Ri → PC ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.30 FR81 Family ● Execution Example CALL:D @R1 ; Bit pattern of the instruction: 1001 1111 0001 0001 LDI:8 #1, R1 ; Instruction placed in delay slot R1 F F F F F 8 0 0 R1 0 0 0 0 0 0 0 1 PC 8 0 0 0 F F F E PC F F F F F 8 0 0 RP x x x x RP 8 0 0 1 0 0 0 2 x x x x Before execution of CALL instruction After branching The instruction placed in delay slot is executed before execution of the branch destination instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.31 FR81 Family 7.31 CMP (Compare Immediate Data and Destination Register) Subtracts the result of the higher 28 bits of 4-bit immediate data with zero extension from the word data in Ri, sets results in the flag of condition code register (CCR). ● Assembler Format CMP #i4, Ri ● Operation Ri - extu(i4) ● Flag Change N C Z C V C C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.32 FR81 Family 7.32 CMP (Compare Word Data in Source Register and Destination Register) Subtracts the word data in Rj from the word data in Ri, sets results in the flag of condition code register (CCR). ● Assembler Format CMP Rj, Ri ● Operation Ri - Rj ● Flag Change N C Z C V C C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.33 FR81 Family 7.33 CMP2 (Compare Immediate Data and Destination Register) Subtracts the result of the higher 28 bits of 4-bit immediate (from -16 to -1) data with minus extension from the word data in Ri, sets results in the flag of condition code register (CCR). ● Assembler Format CMP2 #i4, Ri ● Operation Ri - extn(i4) ● Flag Change N C Z C V C C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.34 FR81 Family 7.34 DIV0S (Initial Setting Up for Signed Division) This is a step division instruction. This command issued for signed division in which multiplication division register (MDL) contains the dividend and the Ri the divisor, with the quotient stored in the MDL and the remainder in multiplication division register (MDH).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.35 FR81 Family 7.35 DIV0U (Initial Setting Up for Unsigned Division) This is a step division command. This command issued for unsigned division in which multiplication division register (MDL) contains the dividend and the Ri the divisor, with the quotient stored in the MDL and the remainder in multiplication division register (MDH).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.36 FR81 Family 7.36 DIV1 (Main Process of Division) This is a step division instruction used for unsigned division. ● Assembler Format DIV1 Ri ● Operation {MDH, MDL} <<= 1 /* 1 bit left shift */ if (D1==1) { MDH + Ri → temp } else { MDH - Ri → temp } if ({D0 ^ D1 ^ C} == 0) { temp → MDH 1 → MDL[0] } ● Flag Change N - Z C V - C C N, V: Unchanged. Z: Set when the result of step division is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.37 FR81 Family 7.37 DIV2 (Correction When Remain is zero) This is a step division instruction used for signed division. ● Assembler Format DIV2 Ri ● Operation if (D1==1) { MDH + Ri → temp } else { MDH - Ri → temp } if (Z==1) { 0 → MDH } ● Flag Change N - Z C V - C C N, V: Unchanged. Z: Set when the result of step division is zero, cleared otherwise. Set according to remainder of division results, not according to quotient.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.38 FR81 Family 7.38 DIV3 (Correction When Remain is zero) This is a step division instruction used for signed division. ● Assembler Format DIV3 ● Operation if (Z==1) { MDL + 1 → MDL } ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.39 FR81 Family 7.39 DIV4S (Correction Answer for Signed Division) This is a step division instruction used for signed division. ● Assembler Format DIV4S ● Operation if (D1==1) { 0 - MDL → MDL } ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.40 FR81 Family 7.40 DMOV (Move Word Data from Direct Address to Register) Transfers, to R13 the word data at the direct address corresponding to 4 times the value of dir8. The value of dir8 × 4 is specified as dir10. ● Assembler Format DMOV @dir10, R13 ● Operation (dir8 × 4) → R13 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.41 FR81 Family 7.41 DMOV (Move Word Data from Register to Direct Address) Transfers word data in R13 to the direct address corresponding to 4 times the value of dir8. The value of dir8 × 4 is specified as dir10. ● Assembler Format DMOV R13,@dir10 ● Operation R13 → (dir8 × 4) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.42 FR81 Family 7.42 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) Transfers the word data at the direct address corresponding to 4 times the value of dir8 to the address indicated in R13. After the data transfer, it increments the value of R13 by 4. The value of dir8 × 4 is specified as dir10.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.43 FR81 Family 7.43 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfers the word data at the address indicated in R13 to the direct address corresponding to 4 times the value dir8. After the data transfer, it increments the value of R13 by 4. The value of dir8 × 4 is specified as dir10.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.44 FR81 Family 7.44 DMOV (Move Word Data from Direct Address to Pre Decrement Register Indirect Address) Decrements the value of R15 by 4, then transfers the word data at the direct address corresponding to 4 times the value of dir8 to the address indicated in R15. The value of dir8 × 4 is specified as dir10. ● Assembler Format DMOV @dir10,@-R15 ● Operation R15 - 4 → R15 (dir8 × 4) → (R15) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.45 FR81 Family 7.45 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) Transfers the word data at the address indicated in R15 to the direct address corresponding to 4 times the value dir8. After the data transfer, it increments the value of R15 by 4. The value of dir8 × 4 is specified as dir10.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.46 FR81 Family 7.46 DMOVB (Move Byte Data from Direct Address to Register) Transfers the byte data at the address indicated by the value dir8 to R13. Uses zeros to extend the higher 24 bits of data. ● Assembler Format DMOVB @dir8, R13 ● Operation (dir8) → R13 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.47 FR81 Family 7.47 DMOVB (Move Byte Data from Register to Direct Address) Transfers the byte data from R13 to the direct address indicated by the value dir8. ● Assembler Format DMOVB R13,@dir8 ● Operation R13 → (dir8) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.48 FR81 Family 7.48 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) Moves the byte data at the direct address indicated by the value dir8 to the address indicated by R13. After the data transfer, it increments the value of R13 by 1. ● Assembler Format DMOVB @dir8,@R13+ ● Operation (dir8) → (R13) R13 + 1 → R13 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.49 FR81 Family 7.49 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) Transfers the byte data at the address indicated by R13 to the direct address indicated by the value dir8. After the data transfer, it increments the value of R13 by 1. ● Assembler Format DMOVB @R13+,@dir8 ● Operation (R13) → (dir8) R13 + 1 → R13 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.50 FR81 Family 7.50 DMOVH (Move Halfword Data from Direct Address to Register) Transfers the half-word data at the direct address corresponding to 2 times the value dir8 to R13. Uses zeros to extend the higher 16 bits of data. The value of dir8 × 2 is specified as dir9. ● Assembler Format DMOVH @dir9, R13 ● Operation (dir8 × 2) → R13 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.51 FR81 Family 7.51 DMOVH (Move Halfword Data from Register to Direct Address) Transfers the half-word data from R13 to the direct address corresponding to 2 times the value dir8. The value of dir8 × 2 is specified as dir9. ● Assembler Format DMOVH R13,@dir9 ● Operation R13 → (dir8 × 2) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.52 FR81 Family 7.52 DMOVH (Move Halfword Data from Direct Address to Post Increment Register Indirect Address) Transfers the half-word data at the direct address corresponding to 2 times the value dir8 to the address indicated by R13. After the data transfer, it increments the value of R13 by 2. The value of dir8 × 2 is specified as dir9.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.53 FR81 Family 7.53 DMOVH (Move Halfword Data from Post Increment Register Indirect Address to Direct Address) Transfers the half-word data at the address indicated by R13 to the direct address corresponding to 2 times the value dir8. After the data transfer, it increments the value of R13 by 2. The value of dir8 × 2 is specified as dir9.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.54 FR81 Family 7.54 ENTER (Enter Function) This instruction is used for stack frame generation processing for high level languages.The value u8 is calculated as an unsigned value. The value of u8 × 4 is specified as u10. ● Assembler Format ENTER #u10 ● Operation R14 → (R15-4) R15 - 4 → R14 R15 - extu(u8 × 4) → R15 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.55 FR81 Family 7.55 EOR (Exclusive Or Word Data of Source Register to Data in Memory) Takes the logical exclusive OR of the word data at memory address Ri and the word data in Rj, stores the results to the memory address corresponding to Ri. ● Assembler Format EOR Rj,@Ri ● Operation (Ri) ^ Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.56 FR81 Family 7.56 EOR (Exclusive Or Word Data of Source Register to Destination Register) Takes the logical exclusive OR of the word data in Ri and the word data in Rj, stores the results to Ri. ● Assembler Format EOR Rj, Ri ● Operation Ri ^ Rj → Ri ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.57 FR81 Family 7.57 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) Takes the logical exclusive OR of the byte data at memory address Ri and the byte datain Rj, stores the results to the memory address corresponding to Ri. ● Assembler Format EORB Rj,@Ri ● Operation (Ri) ^ Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.58 FR81 Family 7.58 EORH (Exclusive Or Halfword Data of Source Register to Data in Memory) Takes the logical exclusive OR of the half-word data at memory address Ri and the halfword data in Rj, stores the results to the memory address corresponding to Ri. ● Assembler Format EORH Rj,@Ri ● Operation (Ri) ^ Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB(bit15) of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.59 FR81 Family 7.59 EXTSB (Sign Extend from Byte Data to Word Data) Extends the byte data indicated by Ri to word data as signed binary value. ● Assembler Format EXTSB Ri ● Operation exts(Ri[7:0]) → Ri [byte → word] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.60 FR81 Family 7.60 EXTSH (Sign Extend from Byte Data to Word Data) Extends the half-word data indicated by Ri to word data as a signed binary value. ● Assembler Format EXTSH Ri ● Operation exts(Ri[15:0]) → Ri [half-word → word] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.61 FR81 Family 7.61 EXTUB (Unsign Extend from Byte Data to Word Data) Extends the byte data indicated by Ri to word data as an unsigned binary value. ● Assembler Format EXTUB Ri ● Operation extu(Ri[7:0]) → Ri [byte → word] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.62 FR81 Family 7.62 EXTUH (Unsign Extend from Byte Data to Word Data) Extends the half-word data indicated by Ri to word data as an unsigned binary value. ● Assembler Format EXTUH Ri ● Operation extu(Ri[15:0]) → Ri [half-word → word] ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.63 FR81 Family 7.63 FABSs (Single Precision Floating Point Absolute Value) Loads the absolute value FRj to FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.64 7.64 FR81 Family FADDs (Single Precision Floating Point Add) FRk is added to FRj, and its result is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.64 FR81 Family ● Calculation result and exception flag FRj +0 +0 -0 +0/(-) -0 +Norm -Norm +INF -INF QNaN SNaN +Norm/(X) -Norm/(X) +INF/(-) -INF/(-) QNaN/(-) QNaN/V -0/(-) +Norm +Norm/(X) *1 *2 -Norm -Norm/(X) *2 *1 FRk +INF -INF QNaN/V -INF/(-) QNaN/V -INF/(-) QNaN SNaN *1: +INF/0,X or -INF/P.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.65 7.65 FR81 Family FBcc (Floating Point Conditional Branch) This is a branching instruction without a delay slot. If conditions specified for each instruction are satisfied, control branches to the address indicated by label17 relative to the program counter (PC). The rel16 value is doubled and its sign is extended. If conditions are not satisfied, no branching occurs.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.65 FR81 Family Table 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.66 7.66 FR81 Family FBcc:D (Floating Point Conditional Branch with Delay Slot) This is a branching instruction having a delay slot. If conditions specified for each instruction are satisfied, control branches to the address indicated by label17 relative to the program counter (PC). The rel16 value is doubled and its sign is extended. If conditions are not satisfied, no branching occurs.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.66 FR81 Family Table 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.67 7.67 FR81 Family FCMPs (Single Precision Floating Point Compare) FRk and FRj are compared, and the result is reflected on the floating point condition code (FCC) of floating point control register (FCR). ● Assembler Format FCMPs FRk, FRj ● Operation FRk - FRj The FCC is set as follows according to the comparison result.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.67 FR81 Family ● EIT Occurrence and Detection An invalid instruction exception (FPU absence error), an FPU exception, or an interrupt is detected.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.68 7.68 FR81 Family FDIVs (Single Precision Floating Point Division) FRk is divided by FRj, and its result is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.69 7.69 FR81 Family FiTOs (Convert from Integer to Single Precision Floating Point) A 32-bit signed integer in FRj is converted into a single-precision floating point value, and it is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.70 7.70 FR81 Family FLD (Single Precision Floating Point Data Load) Loads the value at memory address Rj to FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.71 FR81 Family 7.71 FLD (Single Precision Floating Point Data Load) Loads the value at memory address R13+Rj to FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.72 7.72 FR81 Family FLD (Single Precision Floating Point Data Load) Loads the value at memory address R14+o14 × 4 to FRi. Signed o14 value is calculated. The value in o14 × 4 is specified as disp16.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.73 FR81 Family 7.73 FLD (Single Precision Floating Point Data Load) Loads the value at memory address R15+u14x4 to FRi. Unsigned u14 value is calculated. The value in u14x4 is specified as udisp16.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.74 7.74 FR81 Family FLD (Single Precision Floating Point Data Load) Loads the value at memory address R15 to FRi, and adds 4 to R15.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.75 FR81 Family 7.75 FLD (Load Word Data in Memory to Floating Register) Loads the word data at memory address BP+u16 × 4 to FRi. Unsigned u16 value is calculated. The value in u16 × 4 is specified as udisp18. ● Assembler Format FLD @(BP, udisp18), FRi ● Operation (BP+u16 × 4) → FRi ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.76 7.76 FR81 Family FLDM (Single Precision Floating Point Data Load to Multiple Register) The registers shown on the frlist are sequentially restored from the stack. Registers FR0 to FR15 can be set on the frlist. They are processed in ascending order of register numbers. ● Assembler Format FLDM (frlist) ● Operation The following operations are repeated according to the number of registers specified in the parameter frlist.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.76 FR81 Family ● Instruction Format MSB (n+0) 0 LSB 0 0 0 (n+2) 0 1 1 1 1 1 0 1 1 1 - frlist ● EIT Occurrence and Detection A data access protection violation exception, an invalid instruction exception (a data access error or FPU absence error), or an interrupt is detected. If an exception occurs during repetition, the access that generated the exception is interrupted.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.77 7.77 FR81 Family FMADDs (Single Precision Floating Point Multiply and Add) FRk is multiplied by FRj, and FRi is added to its result and then stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.78 7.78 FR81 Family FMOVs (Single Precision Floating Point Move) Loads the value in FRj to FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.79 FR81 Family 7.79 FMSUBs (Single Precision Floating Point Multiply and Subtract) FRk is multiplied by FRj, and its result is subtracted by FRi and then stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.80 FR81 Family 7.80 FMULs (Single Precision Floating Point Multiply) FRk is multiplied by FRj, and its result is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.81 FR81 Family 7.81 FNEGs (Single Precision Floating Point sign reverse) A sign of FRj value is inverted, and the result is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.82 7.82 FR81 Family FSQRTs (Single Precision Floating Point Square Root) A square root of FRj is calculated, and its result is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.83 FR81 Family 7.83 FST (Single Precision Floating Point Data Store) Loads the value in FRi to memory address Rj.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.84 7.84 FR81 Family FST (Single Precision Floating Point Data Store) Loads the value in FRi to memory address R13+Rj.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.85 FR81 Family 7.85 FST (Single Precision Floating Point Data Store) Loads the value in FRi to memory address R14+o14 × 4. Signed o14 value is calculated. The value in o14 × 4 is specified as disp16.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.86 7.86 FR81 Family FST (Single Precision Floating Point Data Store) Loads the value in FRi to memory address R15+u14 × 4. Unsigned u14 value is calculated. The value in u14 × 4 is specified as udisp16.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.87 FR81 Family 7.87 FST (Single Precision Floating Point Data Store) R15 is subtracted by 4, and the value in FRi is loaded to the memory address identified by new R15.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.88 7.88 FR81 Family FST (Store Word Data in Floating Point Register to Memory) Loads the word data in FRi to memory address BP+u16 × 4. Unsigned u16 value is calculated. The value in u16 × 4 is specified as udisp18. ● Assembler Format FST FRi, @(BP, udisp18) ● Operation FRi → (BP+u16 × 4) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.89 FR81 Family 7.89 FSTM (Single Precision Floating Point Data Store from Multiple Register) The registers shown on frlist are sequentially saved in the stack. Registers FR0 to FR15 can be set on the frlist. They are processed in descending order of register numbers. ● Assembler Format FSTM (frlist) ● Operation The following operations are repeated according to the number of registers specified in the parameter frlist.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.89 FR81 Family ● EIT Occurrence and Detection A data access protection violation exception, an invalid instruction exception (a data access error or FPU absence error), or an interrupt is detected. If an exception occurs during repetition, the access that generated the exception is interrupted. The remaining values of frlist are stored in the register list (RL) of exception status register (ESR), and the exception process is executed.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.90 FR81 Family 7.90 FsTOi (Convert from Single Precision Floating Point to Integer) A single-precision floating point value of FRj is converted into a 32-bit signed integer, and it is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.91 FR81 Family 7.91 FSUBs (Single Precision Floating Point Subtract) FRk is subtracted by FRj, and its result is stored in FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.92 FR81 Family 7.92 INT (Software Interrupt) This is a software interrupt instruction. Reads the vector table for the interrupt vector number u8 to determine the branch destination address, and branches. ● Assembler Format INT #u8 Vector numbers 9 to 13, 64 and 65 are used by emulators for debugging interrupts and therefore the corresponding numbers "INT #9" to "INT #13", "INT #64", "INT #65" should not be used in user programs.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.93 FR81 Family 7.93 INTE (Software Interrupt for Emulator) This software interrupt instruction is used for debugging. It determines the branch destination address by reading interrupt vector number "#9" from the vector table, then branches.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.94 FR81 Family 7.94 JMP (Jump) This is a branching instruction without a delay slot. Branches to the address indicated in Ri. ● Assembler Format JMP @Ri ● Operation Ri → PC ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.95 FR81 Family 7.95 JMP:D (Jump) This is a branching instruction with delay slot. Branches to the address indicated by Ri. ● Assembler Format JMP:D @Ri ● Operation Ri → PC ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.95 FR81 Family ● Execution Example JMP:D @R1 ; Bit pattern of the instruction: 1001 1111 0000 0001 LDI:8 #0FFH, R1 ; Instruction placed in delay slot R1 C 0 0 0 8 0 0 0 R1 0 0 0 0 0 0 F F PC F F 8 0 0 0 0 0 PC C 0 0 0 8 0 0 0 Before execution of JMP instruction After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.96 FR81 Family 7.96 LCALL (Long Call Subroutine) This is a branching instruction without a delay slot. The next instruction address is stored in the return pointer (RP), and then control branches to the address identified by label21 relative to the program counter (PC). The value in rel20 is doubled during address calculation, and its sign is extended.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.97 7.97 FR81 Family LCALL:D (Long Call Subroutine) This is a branching instruction with a delay slot. The next instruction address is stored in the return pointer (RP), and then control branches to the address identified by label21 relative to the program counter (PC). The value in rel20 is doubled during address calculation, and its sign is extended.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.98 FR81 Family 7.98 LD (Load Word Data in Memory to Register) Loads the word data at memory address Rj to Ri. ● Assembler Format LD @Rj, Ri ● Operation (Rj) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.99 FR81 Family 7.99 LD (Load Word Data in Memory to Register) Loads the word data at memory address R13 + Rj to Ri. ● Assembler Format LD @(R13, Rj), Ri ● Operation (R13+Rj) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.100 FR81 Family 7.100 LD (Load Word Data in Memory to Register) Loads the word data at memory address R14 + o8 × 4 to Ri. The value of o8 × 4 is specified as disp10. ● Assembler Format LD @(R14, disp10), Ri ● Operation (R14+o8 × 4) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.101 FR81 Family 7.101 LD (Load Word Data in Memory to Register) Loads the word data at memory address R15 + u4 × 4 to Ri. The value u4 is an unsigned calculation. The value of u4 × 4 is specified as udisp6. ● Assembler Format LD @(R15, udisp6), Ri ● Operation (R15+u4 ×4) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.102 FR81 Family 7.102 LD (Load Word Data in Memory to Register) Loads the word data at memory address R15 to Rj, and adds 4 to the value of R15. If R15 is given as parameter Ri, the value read from the memory will be loaded into memory address R15. ● Assembler Format LD @R15+, Ri ● Operation (R15) → Ri R15 + 4 → R15 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.103 FR81 Family 7.103 LD (Load Word Data in Memory to Register) Loads the word data at memory address BP+u16 × 4 to Ri. Unsigned u16 value is calculated. The value in u16 × 4 is specified as udisp18. ● Assembler Format LD @(BP, udisp18), Ri ● Operation (BP+u16 × 4) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.104 7.104 FR81 Family LD (Load Word Data in Memory to Register) Loads the word data at memory address R15 to dedicated register Rs, and adds 4 to the value of R15. ● Assembler Format LD @R15+, Rs ● Operation (R15) → Rs R15 + 4 → R15 If TBR, SSP, or ESR is specified in user mode or if a non-existing register number is specified in user mode, an invalid instruction exception (system-only register access) is generated.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.104 FR81 Family ● Instruction Format MSB 0 LSB 0 0 0 0 1 1 1 1 0 0 0 Rs ● EIT Occurrence and Detection User mode: An invalid instruction exception (system-only register access) is generated. A data access protection violation exception, an invalid instruction exception (data access error), or an interrupt is detected.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.105 7.105 FR81 Family LD (Load Word Data in Memory to Program Status Register) Loads the word data at memory address R15 to the program status (PS), and adds 4 to the value of R15. ● Assembler Format LD @R15+, PS ● Operation (R15) → PS R15 + 4 → R15 The contents of system status register (SSR) cannot be changed by this instruction regardless of the selected operation mode.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.105 FR81 Family ● Instruction Format MSB 0 LSB 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 ● EIT Occurrence and Detection A data access protection violation exception, an invalid instruction exception (data access error), or an interrupt is detected. If the interrupt level mask register (ILM) or interrupt enable flag (I) is changed, an interrupt is detected using the changed values.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.106 7.106 FR81 Family LDI:20 (Load Immediate 20bit Data to Destination Register) Extends the 20-bit immediate data with 12 zeros in the higher bits, loads to Ri. ● Assembler Format LDI:20 #i20, Ri ● Operation extu(i20) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.107 7.107 FR81 Family LDI:32 (Load Immediate 32 bit Data to Destination Register) Loads 1 word of immediate data to Ri. ● Assembler Format LDI:32 #i32, Ri ● Operation i32 → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.108 7.108 FR81 Family LDI:8 (Load Immediate 8bit Data to Destination Register) Extends the 8-bit immediate data with 24 zeros in the higher bits, loads to Ri. ● Assembler Format LDI:8 #i8, Ri ● Operation extu(i8) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.109 7.109 FR81 Family LDM0 (Load Multiple Registers) The LDM0 instruction stores the word data from the address R15 to the registers in the range R0 to R7 as members of the parameter reglist and repeats the operation of adding 4 to R15. Registers are processed in ascending numerical order. ● Assembler Format LDM0 (reglist) Registers from R0 to R7 are separated in reglist, multiple register are arranged and specified.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.109 FR81 Family ● Classification Other instructions ● Execution Cycles If "n" is the number of registers specified in the parameter reglist, the execution cycles required are as follows.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 7.110 FR81 Family LDM1 (Load Multiple Registers) Loads the word data of address R15 to multiple registers R8 to R15 specified in reglist, repeats the operation of adding 4 to R15. Registers are processed in ascending numerical order. If R15 is specified in the parameter reglist, the final contents of R15 will be read from memory.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.110 FR81 Family ● Classification Other instructions ● Execution Cycles If "n" is the number of registers specified in the parameter reglist the execution cycles required are as follows.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.111 7.111 FR81 Family LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address Rj, loads to Ri. ● Assembler Format LDUB @Rj, Ri ● Operation extu((Rj)) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.112 7.112 FR81 Family LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address R13 + Rj, loads to Ri. ● Assembler Format LDUB @(R13, Rj), Ri ● Operation extu((R13+Rj)) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.113 7.113 FR81 Family LDUB (Load Byte Data in Memory to Register) Extends with zeros the byte data at memory address 14 + o8, loads to Ri. The value o8 is a signed calculation. The value of o8 is specified in disp8. ● Assembler Format LDUB @(R14, disp8), Ri ● Operation extu((R14+o8)) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.114 7.114 FR81 Family LDUB (Load Byte Data in Memory to Register) Loads the byte data at memory address BP+u16 to Ri. Unsigned u16 value is calculated. The value in u16 is specified as udisp16. ● Assembler Format LDUB @(BP, udisp16), Ri ● Operation (BP+u16) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.115 FR81 Family 7.115 LDUH (Load Halfword Data in Memory to Register) Extends with zeros the half-word data at memory address Rj, loads to Ri. ● Assembler Format LDUH @Rj, Ri ● Operation extu((Rj)) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.116 FR81 Family 7.116 LDUH (Load Halfword Data in Memory to Register) Extends with zeros the half-word data at memory address R13 + Rj, loads to Ri. ● Assembler Format LDUH @(R13, Rj), Ri ● Operation extu((R13+Rj)) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.117 FR81 Family 7.117 LDUH (Load Halfword Data in Memory to Register) Extends with zeros the half-word data at memory address R14 + o8 × 2, loads to Ri. The value o8 is a signed calculation. The value of o8 × 2 is specified in disp9. ● Assembler Format LDUH @(R14, disp9), Ri ● Operation extu((R14+o8 × 2)) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.118 FR81 Family 7.118 LDUH (Load Halfword Data in Memory to Register) Loads the half word data at memory address BP+u16 × 2 to Ri. Unsigned u16 value is calculated. The value in u16 × 2 is specified as udisp17. ● Assembler Format LD @(BP, udisp17), Ri ● Operation (BP+u16 × 2) → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.119 7.119 FR81 Family LEAVE (Leave Function) This instruction is used for stack frame release processing for high level languages. ● Assembler Format LEAVE ● Operation R14+4 → R15 (R15-4) → R14 ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.120 7.120 FR81 Family LSL (Logical Shift to the Left Direction) Makes a logical left shift of the word data in Ri by Rj bits, stores the result to Ri. Only the lower 5 bits of Rj, which designates the size of the shift, are valid and the shift range is 0 to 31 bits. ● Assembler Format LSL Rj, Ri ● Operation Ri << Rj → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.121 7.121 FR81 Family LSL (Logical Shift to the Left Direction) Makes a logical left shift of the word data in Ri by u4 bits, stores the result to Ri. ● Assembler Format LSL #u4, Ri ● Operation Ri << u4 → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V: Unchanged. C: Holds the bit value shifted last.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.122 7.122 FR81 Family LSL2 (Logical Shift to the Left Direction) Makes a logical left shift of the word data in Ri by u4+16 bits, stores the result to Ri. ● Assembler Format LSL2 #u4, Ri ● Operation Ri << {u4+16} → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V: Unchanged. C: Holds the bit value shifted last.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.123 7.123 FR81 Family LSR (Logical Shift to the Right Direction) Makes a logical right shift of the word data in Ri by Rj bits, stores the result to Ri. Only the lower 5 bits of Rj, which designates the size of the shift, are valid and the shift range is 0 to 31 bits. ● Assembler Format LSR Rj, Ri ● Operation Ri >> Rj → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.124 7.124 FR81 Family LSR (Logical Shift to the Right Direction) Makes a logical left shift of the word data in Ri by u4 bits, stores the result to Ri. ● Assembler Format LSR #u4, Ri ● Operation Ri >> u4 → Ri ● Flag Change N C Z C V - C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V: Unchanged. C: Holds the bit value shifted last.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.125 7.125 FR81 Family LSR2 (Logical Shift to the Right Direction) Makes a logical left shift of the word data in Ri by u4+16 bits, stores the result to Ri. ● Assembler Format LSR2 #u4, Ri ● Operation Ri >> {u4+16} → Ri ● Flag Change N C Z C V - C C N: Cleared. Z: Set when the operation result is zero, cleared otherwise. V: Unchanged. C: Holds the bit value shifted last.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.126 7.126 FR81 Family MOV (Move Word Data in Source Register to Destination Register) Moves the word data in Rj to Ri. ● Assembler Format MOV Rj, Ri ● Operation Rj → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.127 7.127 FR81 Family MOV (Move Word Data in Source Register to Destination Register) Moves the word data in dedicated register Rs to general-purpose register Ri. ● Assembler Format MOV Rs, Ri ● Operation Rs → Ri If the number of a non-existent dedicated register is given as Rs, undefined data will be transferred. ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.128 7.128 FR81 Family MOV (Move Word Data in Program Status Register to Destination Register) Moves the word data in the program status (PS) to general-purpose register Ri. ● Assembler Format MOV PS, Ri ● Operation PS → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.129 7.129 FR81 Family MOV (Move Word Data in Source Register to Destination Register) Moves the word data of general-purpose register Ri to dedicated register Rs. ● Assembler Format MOV Ri, Rs ● Operation Ri → Rs If TBR, SSP, or ESR is specified in user mode or if a number without a dedicated register is specified for "RS", it generates an invalid instruction exception (system-only register access). There is no restriction in privilege mode.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.129 FR81 Family ● EIT Occurrence and Detection User mode: An invalid instruction exception (system-only register access) is generated and an interrupt is detected. Privilege mode: An interrupt is detected.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.130 7.130 FR81 Family MOV (Move Word Data in Source Register to Program Status Register) Stores the word data of general-purpose register Ri to program status (PS). ● Assembler Format MOV Ri, PS ● Operation Ri → PS The contents of system status register (SSR) cannot be changed by this instruction regardless of the selected operation mode. If this instruction is executed in user mode, only the D1, D0, N, Z, V, and C flags can be changed.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.130 FR81 Family ● Instruction Format MSB 0 LSB 0 0 0 0 1 1 1 0 0 0 1 Ri ● EIT Occurrence and Detection An interrupt is detected.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.131 7.131 FR81 Family MOV (Move Word Data in General Purpose Register to Floating Point Register) The value in Rj is transferred to FRi.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.132 FR81 Family 7.132 MOV (Move Word Data in Floating Point Register to General Purpose Register) The value in FRi is transferred to Rj.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.133 7.133 FR81 Family MUL (Multiply Word Data) Multiplies the word data in Rj by the word data in Ri as signed numbers, and stores the resulting signed 64-bit data with the higher word in the multiplication/division register (MDH), and the lower word in the multiplication/division register (MDL).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.134 7.134 FR81 Family MULH (Multiply Halfword Data) Multiplies the half-word data in the lower 16 bits of Rj by the half-word data in the lower 16 bits of Ri as signed numbers, and stores the resulting signed 32-bit data in the multiplication/division register (MDL). The multiplication/division register (MDH) is undefined.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.135 7.135 FR81 Family MULU (Multiply Unsigned Word Data) Multiplies the word data in Rj by the word data in Ri as unsigned numbers and stores the resulting unsigned 64-bit data with the higher word in the multiplication/division register (MDH), and the lower word in the multiplication/division register (MDL).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.136 7.136 FR81 Family MULUH (Multiply Unsigned Halfword Data) Multiplies the half-word data in the lower 16 bits of Rj by the half-word data in the lower 16 bits of Ri as unsigned numbers, and stores the resulting unsigned 32-bit data in the multiplication/division register (MDL). The multiplication/division register (MDH) is undefined.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.137 7.137 FR81 Family NOP (No Operation) This instruction performs no operation. ● Assembler Format NOP ● Operation No operation ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.138 7.138 FR81 Family OR (Or Word Data of Source Register to Data in Memory) Takes the logical OR of the word data at memory address Ri and the word data in Rj, stores the results to the memory address corresponding to Ri. ● Assembler Format OR Rj,@Ri ● Operation (Ri) | Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.139 7.139 FR81 Family OR (Or Word Data of Source Register to Destination Register) Takes the logical OR of the word data in Ri and the word data in Rj, stores the results to Ri. ● Assembler Format OR Rj, Ri ● Operation Ri | Rj → Ri ● Flag Change N C Z C V - C - N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise. V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.140 7.140 FR81 Family ORB (Or Byte Data of Source Register to Data in Memory) Takes the logical OR of the byte data at memory address Ri and the byte data in Rj, stores the results to the memory address corresponding to Ri. ● Assembler Format ORB Rj,@Ri ● Operation (Ri) | Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB(bit7) of the operation result is "1", cleared when the MSB(bit7) is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.141 7.141 FR81 Family ORCCR (Or Condition Code Register and Immediate Data) Takes the logical OR of the byte data in the condition code register (CCR) and the immediate data, and returns the results in to the CCR. ● Assembler Format ORCCR #u8 ● Operation User mode: CCR | (u8 & CFH) → CCR Privilege mode: CCR | u8 → CCR In user mode, a request to rewrite the stack flag (S) or the interrupt enable flag (I) is ignored.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.141 FR81 Family ● EIT Occurrence and Detection An interrupt is detected (the value of I flag after instruction execution is used).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.142 7.142 FR81 Family ORH (Or Halfword Data of Source Register to Data in Memory) Takes the logical OR if the half-word data at memory address Ri and the half-word data in Rj, stores the results to the memory address corresponding to Ri. ● Assembler Format ORH Rj,@Ri ● Operation (Ri) | Rj → (Ri) ● Flag Change N C Z C V - C - N: Set when the MSB(bit15) of the operation result is "1", cleared when the MSB is "0".
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.143 7.143 FR81 Family RET (Return from Subroutine) This is a branching instruction without a delay slot. Branches to the address indicated by the return pointer(RP). Used for return from Subroutine. ● Assembler Format RET ● Operation RP → PC ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.144 7.144 FR81 Family RET:D (Return from Subroutine) This is a branching instruction with a delay slot. Branches to the address indicated by the return pointer (RP). Used for return from Subroutine. ● Assembler Format RET:D ● Operation RP → PC ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.145 7.145 FR81 Family RETI (Return from Interrupt) Loads data from the stack indicated by system stack pointer (SSP), to the program counter (PC) and program status (PS), and retakes control from the EIT operation handler.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.145 FR81 Family ● Classification Non-Delayed Branching instruction, FR81 updating ● Execution Cycles 1+2b cycles ● Instruction Format MSB 1 LSB 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 ● EIT Occurrence and Detection User mode: An invalid instruction exception (privilege instruction execution) is generated. Privilege mode: A data access protection violation exception, an invalid instruction exception (data access error), or an interrupt is detected.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.146 FR81 Family 7.146 SRCH0 (Search First Zero bit position distance From MSB) This is a "0" search instruction used for bit searching. Takes a comparison of word data in Ri from MSB (bit31) and "0", stores the distance in Ri from the first "0" that is found and bit MSB (bit31). ● Assembler Format SRCH0 Ri ● Operation search_zero(Ri) → Ri If "0" bit is not found (in case all word data of Ri is "1" bit), 32 is stored in Ri.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.147 FR81 Family 7.147 SRCH1 (Search First One bit position distance From MSB) This is a "1" search instruction used for bit searching. Takes a comparison of word data in Ri from MSB (bit31) and "1", stores the distance in Ri from the first "1" that is found and bit MSB(bit31). ● Assembler Format SRCH1 Ri ● Operation search_one(Ri) → Ri If "1" bit is not found (in case all word data of Ri is "0" bit), 32 is stored in Ri.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.148 FR81 Family 7.148 SRCHC (Search First bit value change position distance From MSB) This is a Change point search instruction used for bit searching. Takes a comparison of data in Ri with MSB (bit31), stores in Ri the distance from the first varying bit value that is found and bit MSB (bit31). ● Assembler Format SRCHC Ri ● Operation search_change(Ri) → Ri If the values of all bits are the same, 32 is stored in Ri.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.148 FR81 Family ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.149 FR81 Family 7.149 ST (Store Word Data in Register to Memory) Loads word data in Ri to memory address Rj. ● Assembler Format ST Ri,@Rj ● Operation Ri → (Rj) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.150 FR81 Family 7.150 ST (Store Word Data in Register to Memory) Loads the word data in Ri to memory address R13 + Rj. ● Assembler Format ST Ri,@(R13, Rj) ● Operation Ri → (R13+Rj) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.151 FR81 Family 7.151 ST (Store Word Data in Register to Memory) Loads the word data in Ri to memory address R14 + o8 × 4. The value o8 is a signed calculation. The value of o8 × 4 is specified in disp10. ● Assembler Format ST Ri,@(R14, disp10) ● Operation Ri → (R14+o8 × 4) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.152 FR81 Family 7.152 ST (Store Word Data in Register to Memory) Loads the word data in Ri to memory address R15 + u4 × 4. The value u4 is an unsigned calculation. The value of u4 × 4 is specified in udisp6. ● Assembler Format ST Ri,@(R15, udisp6) ● Operation Ri → (R15+u4 × 4) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.153 FR81 Family 7.153 ST (Store Word Data in Register to Memory) Subtracts 4 from the value of R15, stores the word data in Ri to the memory address indicated by the new value of R15. If R15 is given as the parameter Ri, the data transfer will use the value of R15 before subtraction. ● Assembler Format ST Ri,@-R15 ● Operation R15 - 4 → R15 Ri → (R15) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.154 FR81 Family 7.154 ST (Store Word Data in Register to Memory) Loads the word data in Ri to memory address BP+u16 × 4. Unsigned u16 value is calculated. The value in u16 × 4 is specified as udisp18. ● Assembler Format ST Ri, @(BP, udisp18) ● Operation Ri → (BP+u16 × 4) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.155 7.155 FR81 Family ST (Store Word Data in Register to Memory) Subtracts 4 from the value R15, stores the word data in dedicated register Rs to the memory address indicated by the new value of R15. ● Assembler Format ST Rs,@-R15 ● Operation R15 - 4 → R15 Rs → (R15) If the number of a non-existent dedicated register is specified in parameter Rs, the read value will be ignored. ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.156 7.156 FR81 Family ST (Store Word Data in Program Status Register to Memory) Subtracts 4 from the value of R15, stores the word data in the program status (PS) to the memory address indicated by the new value of R15. ● Assembler Format ST PS,@-R15 ● Operation R15 - 4 → R15 PS → (R15) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.157 7.157 FR81 Family STB (Store Byte Data in Register to Memory) Stores the byte data in Ri to memory address Rj. ● Assembler Format STB Ri,@Rj ● Operation Ri → (Rj) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.158 7.158 FR81 Family STB (Store Byte Data in Register to Memory) Stores the byte data in Ri to memory address R13 + Rj. ● Assembler Format STB Ri,@(R13, Rj) ● Operation Ri → (R13+Rj) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.159 7.159 FR81 Family STB (Store Byte Data in Register to Memory) Stores the byte data in Ri to memory address R14 + o8. The value o8 is a signed calculation. The value of o8 is specified in disp8. ● Assembler Format STB Ri,@(R14, disp8) ● Operation Ri → (R14+o8) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.160 7.160 FR81 Family STB (Store Byte Data in Register to Memory) Loads the byte data in Ri to memory address BP+u16. Unsigned u16 value is calculated. The value in u16 is specified as udisp16. ● Assembler Format STB Ri, @(BP, udisp16) ● Operation Ri → (BP+u16) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.161 FR81 Family 7.161 STH (Store Halfword Data in Register to Memory) Stores the half-word data in Ri to memory address Rj. ● Assembler Format STH Ri,@Rj ● Operation Ri → (Rj) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.162 FR81 Family 7.162 STH (Store Halfword Data in Register to Memory) Stores the half-word data in Ri to memory address R13 + Rj. ● Assembler Format STH Ri,@(R13, Rj) ● Operation Ri → (R13+Rj) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.163 FR81 Family 7.163 STH (Store Halfword Data in Register to Memory) Stores the half-word data in Ri to memory address R14 + o8 × 2. The value of o8 × 2 is specified in disp9. ● Assembler Format STH Ri,@(R14, disp9) ● Operation Ri → (R14+o8×2) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.164 FR81 Family 7.164 STH (Store Halfword Data in Register to Memory) Loads the half word data in Ri to memory address BP+u16 × 2. Unsigned u16 value is calculated. The value in u16 × 2 is specified as udisp17. ● Assembler Format STB Ri, @(BP, udisp17) ● Operation Ri → (BP+u16 × 2) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.165 7.165 FR81 Family STILM (Set Immediate Data to Interrupt Level Mask Register) Transfers the immediate data to the interrupt level mask register (ILM) in the program status (PS). ● Assembler Format STILM #u8 ● Operation if (ILM < 16) u8 → ILM else if (u8 < 16) u8+16 → ILM else u8 → ILM This is a privilege instruction, which is only available in privilege mode.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.165 FR81 Family ● Execution Cycles 1 cycle ● Instruction Format MSB 1 LSB 0 0 0 0 1 1 1 u8 ● EIT Occurrence and Detection User mode: Used to generate an invalid instruction exception (privilege instruction execution). Privilege mode: An interrupt is detected (ILM after instruction execution is used).
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.166 7.166 FR81 Family STM0 (Store Multiple Registers) The STM0 instruction stores the word data from multiple registers specified in reglist (from R0 to R7) and repeats the operation of storing the result in address R15 after subtracting the value of 4 from R15. Registers are processed in ascending order. ● Assembler Format STM0 (reglist) Registers from R0 to R7 are separated by "," , arranged and specified in reglist.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.166 FR81 Family ● Classification Other instructions ● Execution Cycles If "n" is the number of registers specified in the parameter reglist, the execution cycles required are as follows.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.167 7.167 FR81 Family STM1 (Store Multiple Registers) The STM1 instruction stores the word data from multiple registers specified in reglist (from R8 to R15) and repeats the operation of storing the result in address R15 after subtracting the value of 4 from R15. Registers are processed in ascending order. If R15 is specified in the parameter reglist, the contents of R15 retained before the instruction is executed will be written to memory.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.167 FR81 Family ● Classification Other instructions ● Execution Cycles If "n" is the number of registers specified in the parameter reglist, the execution cycles required are as follows.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.168 7.168 FR81 Family SUB (Subtract Word Data in Source Register from Destination Register) Subtracts the word data in Rj from the word data in Ri, stores the results to Ri. ● Assembler Format SUB Rj, Ri ● Operation Ri - Rj → Ri ● Flag Change N C Z C V C C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is zero, cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.169 7.169 FR81 Family SUBC (Subtract Word Data in Source Register and Carry bit from Destination Register) Subtracts word data in Rj and carry flag (C) from Ri, stores the results to Ri. ● Assembler Format SUBC Rj, Ri ● Operation Ri - Rj - C → Ri ● Flag Change N C Z C V C C C N: Set when the MSB of the operation result is "1", cleared when the MSB is "0". Z: Set when the operation result is "0", cleared otherwise.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.170 7.170 FR81 Family SUBN (Subtract Word Data in Source Register from Destination Register) Subtracts the word data in Rj from the word data in Ri, stores results to Ri without changing the flag settings. ● Assembler Format SUBN Rj, Ri ● Operation Ri - Rj → Ri ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.171 7.171 FR81 Family XCHB (Exchange Byte Data) Exchanges the contents of the byte address indicated by Rj and those indicated by Ri. The lower 8 bits of data originally at Ri are transferred to the byte address indicated by Rj and the data originally at Rj is extended with zeros and transferred to Ri. ● Assembler Format XCHB @Rj, Ri ● Operation Ri → TEMP extu((Rj)) → Ri TEMP → (Rj) ● Flag Change N - Z - V - C - N, Z, V, C: Unchanged.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7.
APPENDIX It includes Instruction Lists and Instruction Maps of FR81 Family.
APPENDIX APPENDIX A Instruction Lists APPENDIX A FR81 Family Instruction Lists It includes Instruction Lists of FR81 Family CPU. A.1 Meaning of Symbols A.2 Instruction Lists A.
FR81 Family A.1 APPENDIX A APPENDIX Instruction Lists Meaning of Symbols This section describes the meaning of symbols used in the Instruction Lists and Detailed Execution Instructions has been explained. A.1.1 Mnemonic and Operation Columns These are the symbols used in Mnemonic and Operation columns of Instruction Lists as well as assembler format of Detailed Execution Instructions and operation. i4 It is 4-bit immediate data.
APPENDIX APPENDIX A Instruction Lists FR81 Family u4 unsigned 4-bit immediate data, range 0 (0H) to 15 (FH) u8 unsigned 8-bit immediate data, range 0 (00H) to 255 (FFH) u10 unsigned 10-bit immediate data, range 0 (000H) to 1020 (3FCH) in multiples of 4 udisp6 unsigned 6-bit address values, range 0 (00H) to 60 (3CH) in multiples of 4 udisp16 unsigned 16-bit address values, range 0 (0000H) to 65535 (FFFFH), range 0 (0000H) to 65532 (FFFCH) in multiples of 4 udisp17 unsigned 17-bit address values, range 0
FR81 Family APPENDIX A APPENDIX Instruction Lists dir9 unsigned 9-bit address values, range 0 (000H) to 510 (1FEH) in multiples of 2 dir10 unsigned 10-bit address values, range 0 (000H) to 1020 (3FCH)in multiples of 4 label9 branch address, range 256 (100H) to 254 (0FEH) in multiples of 2 for the value of Program Counter (PC) +2 label12 branch address, range -2048 (800H) to 2046 (7FEH) in multiples of 2 for the value of Program Counter (PC) +2 label17 branch address, range -65536 (10000H) to 65534 (0FF
APPENDIX APPENDIX A Instruction Lists FR81 Family Ri, Rj Indicates General-purpose Registers (R0 to R15) Table A.1-2 Specification of General-purpose register based on Rj/Ri Ri / Rj 0000 0001 0010 0011 0100 0101 0110 0111 Register R0 R1 R2 R3 R4 R5 R6 R7 Ri / Rj 1000 1001 1010 1011 1100 1101 1110 1111 Register R8 R9 R10 R11 R12 R13 R14 R15 Rs Indicates Dedicated Registers (TBR, RP, USP, SSP, MDH, MDL, BP, FCR, ESR, DBR) Table A.
FR81 Family APPENDIX A APPENDIX Instruction Lists FRi, FRj, FRk Indicates Floating Point Registers (FR0 to FR15) Table A.1-4 Floating Point Register based on FRi/FRj/FRk FRi/FRj/FRk 0000 0001 0010 0011 0100 0101 0110 0111 Register FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FRi/FRj/FRk 1000 1001 1010 1011 1100 1101 1110 1111 Register FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 (reglist) Indicates 8-bit Register list. General purpose register corresponding to each bit value can be specified. Table A.
APPENDIX APPENDIX A Instruction Lists FR81 Family (frlist) Indicates 16-bit Register list. Floating Point Registers (FR0 to FR15) corresponding to each bit value can be specified. Table A.1-7 Correspondence between frlist bit of FLDM Instruction and Floating Point Registers frlist bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Register FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 frlist bit8 bit9 bit10 bit11 bit12 bit13 bit14 bit15 Register FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 Table A.
FR81 Family APPENDIX A APPENDIX Instruction Lists is "0" and a minus extension is performed if MSB is "1". & Indicates logical calculation of each bit (AND) | Indicates the logical sum of each bit (OR) ^ Indicates Dedicated Logical Sum of each bit (EXOR) () Indicates specification of indirect address. It is address memory read/write value of the Register or formula within ( ). {} Indicate the calculation priority.
APPENDIX APPENDIX A Instruction Lists FR81 Family TYPE-B 2-digit hexadecimal value represents 4 bits of OP code as higher 1 digit and "0" for lower digit. TYPE-E, TYPE-H, TYPE-I, TYPE-J, TYPE-K 3-digit hexadecimal value represents 12-bit OP code. TYPE-F 2-digit hexadecimal value represents 8 bits with 3-bit 000B added below 5-bit OP code. TYPE-L, TYPE-N 4-digit hexadecimal value represents 16 bits with 2-bit 00B added below 14-bit OP code. TYPE-M 4-digit hexadecimal value represents 16-bit OP code. A.
FR81 Family APPENDIX A APPENDIX Instruction Lists c An interlock will be applied when the immediately next Instruction refers to Multiplication/Division Register (MDH) and the number of execution cycles will be increased to 2. Otherwise it will be 1 cycle. d There will be 2 cycles when pre-fetching of Instruction in the Pre-fetch Buffer is not carried out. Minimum value is 1 cycle. A.1.
APPENDIX APPENDIX A A.2 Instruction Lists FR81 Family Instruction Lists This part indicates Instruction Lists of FR81 Family CPU. There are a total of 231 instructions in FR81 Family CPU. These instructions are divided into the following 21 categories.
FR81 Family APPENDIX A APPENDIX Instruction Lists Table A.
APPENDIX APPENDIX A Instruction Lists FR81 Family Table A.2-4 Bit Operation Instructions (8 Instructions) Mnemonic Format OP CYC FLAG NZVC RMW BANDL #u4, @Ri C 80 1+2a ---- ❍ (Ri) & {F0H+u4} → (Ri) Lower 4- bit 7.
FR81 Family APPENDIX A APPENDIX Instruction Lists Table A.
APPENDIX APPENDIX A Instruction Lists FR81 Family Table A.
FR81 Family APPENDIX A APPENDIX Instruction Lists Table A.
APPENDIX APPENDIX A Instruction Lists FR81 Family Table A.
FR81 Family APPENDIX A APPENDIX Instruction Lists • The field rel8 in TYPE-D Instruction Format and the field rel11 in TYPE-F Format have the following relation to the values of label9, label12 in assembly notation. rel8 = (label9-PC-2)/2 rel11 = (label12-PC-2)/2 • The field rel20 in TYPE-I Instruction Format has the following relation to the values of label21 in assembly notation. rel20 = (labe21-PC-4)/2 Table A.
APPENDIX APPENDIX A Instruction Lists FR81 Family • Delayed Branching Instructions are branched after always executing the following Instruction (the Delay Slot). • The field rel8 in TYPE-D instruction format and the field rel11 in TYPE-D format have the following relation to the values label9, label12 in assembly notation. rel8 = (label9-PC-2)/2 rel11 = (label12-PC-2)/2 • The field rel20 in TYPE-I Instruction Format has the following relation to the values of label21 in assembly notation.
FR81 Family APPENDIX A APPENDIX Instruction Lists Table A.2-14 Bit Search Instructions (3 Instructions) Mnemonic Format OP CYC FLAG NZVC RMW SRCH0 Ri SRCH1 Ri SRCHC Ri E E E 97-C 97-D 97-E 1 1 1 ---------- - Operation search_zero(Ri) → Ri search_one(Ri) → Ri search_change(Ri) → Ri Remarks Reference Searches first 0 Bit Searches first 1 Bit Searches first change 7.110 7.111 7.112 Table A.
APPENDIX APPENDIX A Instruction Lists FR81 Family Table A.2-16 FPU Memory Load Instructions (7 Instructions) Format OP CYC FCC ELGU RMW K K L L 07-C 07-E 07-D0 07-D4 a a a a ------------- - FLD @R15+, FRi L 07-D8 a ---- - FLD @(BP, udisp18), FRi J 07-7 a ---- Mnemonic FLD FLD FLD FLD @Rj, FRi @(R13, Rj), FRi @(R14, disp16), FRi @(R15, udisp16), FRi FLDM (frlist) N 07-DC *1 ---- Operation (Rj) → FRi Remarks Reference Word Word Word Word 7.70 7.71 7.72 7.
FR81 Family APPENDIX A APPENDIX Instruction Lists Table A.
APPENDIX APPENDIX A Instruction Lists FR81 Family Table A.
FR81 Family APPENDIX A APPENDIX Instruction Lists Table A.
APPENDIX APPENDIX A A.3 Instruction Lists FR81 Family List of Instructions that can be positioned in the Delay Slot This section shows the Instructions List that can be positioned in the delay slot of Delay Branching Instruction.
FR81 Family APPENDIX A LDUH @Rj, Ri LDUH @(R13, Rj), Ri LDUH @(R14, disp9), Ri LDUB @Rj, Ri LDUB @(R13, Rj), Ri LDUB @(R14, disp8), Ri ST Ri, @Rj ST Ri, @(R13, Rj) ST Ri, @(R14, disp10) ST Ri, @(R15, udisp6) ST Ri, @-R15 ST Rs, @-R15 STH Ri, @Rj STH Ri, @(R13, Rj) STH Ri, @(R14, disp9) STB Ri, @Rj STB Ri, @(R13, Rj) STB Ri, @(R14, disp8) APPENDIX Instruction Lists ● Memory Store Instructions ST PS, @-R15 ● Inter-Register Transfer Instructions MOV Rj, Ri MOV Rs, Ri MOV PS, Ri MOV Ri
APPENDIX APPENDIX B Instruction Maps APPENDIX B FR81 Family Instruction Maps It includes instruction maps of FR81 Family CPU. B.1 Instruction Maps B.
CM71-00105-1E 0 1 ST Ri,@ (R14, disp10) LDUH @(R14, disp9),Ri STH Ri,@(R14, disp9) LDUB @(R14, disp8),Ri 8 FUJITSU MICROELECTRONICS LIMITED F #u8 ENTER #u10 E INT DMOVH @d9, DMOVH @R13+ @R13+, @ d9 DMOVB DMOVB @d8, @R13+ @R13+, @ d8 D DMOV DMOV @d10,@–R15 @R15+,@d10 DMOV DMOV @d10,@R13+ @R13+,@d10 B C 9 ORCCR #u8 OR Rj, Ri BORH #u4,@Ri BORL #u4,@Ri ANDB Rj,@Ri ANDH Rj,@Ri STM1 (reglist) STM0 (reglist) LDM1 (reglist) LDM0 (reglist) BT STH #u4,@Ri A EORH Rj,@Ri Refer to APPE
APPENDIX APPENDIX B B.2 Instruction Maps FR81 Family Extension Instruction Maps The following shows an instruction map when the operation code consists of 12 or more bits. Instructions with a 12-bit operation code (OP), which is divided into 8 higher bits and 4 lower bits are shown in Table B.2-1. Table B.
FR81 Family APPENDIX B APPENDIX Instruction Maps Instructions with 16-bit and 14-bit operation codes (OP), each of which is divided into 8 higher bits and 8 lower bits are shown in Tables Table B.2-2 and Table B.2-3. An instruction with a 14-bit operation code is padded to the MSB side to convert the 14-bit operation code to a 16-bit operation code. Table B.
APPENDIX APPENDIX B Instruction Maps FR81 Family Table B.
FR81 Family APPENDIX APPENDIX C Supplemental Explanation about FPU Exception Processing APPENDIX C C.1 Supplemental Explanation about FPU Exception Processing Conformity with IEEE754-1985 Standard The FR81 Family CPU conforms to the IEEE754-1985 standard (hereinafter referred to as "IEEE754"), excluding the following. 1.
APPENDIX APPENDIX C Supplemental Explanation about FPU Exception Processing C.2 FR81 Family FPU Exceptions FPU exceptions are classified into six types: five exceptions (Inexact, Underflow, Overflow, Division by Zero, and Invalid Calculation), which are defined in IEEE754, and an exception that is generated when an unnormalized number is input. Whether or not to generate those calculation exceptions can be specified using the FPU control register (FCR.EEF).
FR81 Family APPENDIX APPENDIX C Supplemental Explanation about FPU Exception Processing 3. Overflow exception (Overflow) This exception occurs when, during calculation, the exponent exceeds the maximum that can be expressed in the specified format. If this exception occurs, the following operations are carried out. [FCR:EEF:O=1] Writing to the floating point register is prohibited. The FCR:CEF:O flag is set to generate this exception. [FCR:EEF:O=0] As shown in the following Table C.
APPENDIX APPENDIX C Supplemental Explanation about FPU Exception Processing FR81 Family [FCR:EEF:X=0] The calculation result is stored in the floating point register. The FCR:ECF:X flag is set. 6. Unnormalized Number Input exception (Denormalized Number Input) This exception occurs when an unnormalized number is specified in the input operand. If this exception occurs, the following operations are carried out. [FCR:EEF:D=1] Writing to the floating point register is prohibited.
FR81 Family APPENDIX APPENDIX C Supplemental Explanation about FPU Exception Processing Table C.3-1 Rounding Mode and Rounding Processing of Significand Rounding mode (FCR.RM) 00B (Latest value) S≥0 "p+1" if "r^!s^LSB" or "r^s" is true S<0 "p+1" if "r^!s^LSB" or "r^s" is true 01B (Zero) 10B (+∞) "p+1" if "r∪s" is true 11B (-∞) "p+1" if "r∪s" is true The blank column means that the "p" value is used as the result.
APPENDIX APPENDIX C Supplemental Explanation about FPU Exception Processing 460 FUJITSU MICROELECTRONICS LIMITED FR81 Family CM71-00105-1E
FR81 Family INDEX The index follows on the next page. This is listed in alphabetic order.
FR81 Family Index Numerics A 20-bit Addressing 20-bit Addressing Area & 32-bit Addressing Area ............................................................11 32-bit Addressing 20-bit Addressing Area & 32-bit Addressing Area ............................................................11 Access Data Access ....................................................... 14 Program Access ................................................. 14 ADD ADD (Add 4bit Immediate Data to Destination Register).................
FR81 Family Arithmetic shift ASR (Arithmetic shift to the Right Direction) ..................................................131, 133 ASR2 (Arithmetic shift to the Right Direction) ..........................................................135 ASR ASR (Arithmetic shift to the Right Direction) ..................................................131, 133 ASR2 (Arithmetic shift to the Right Direction) ..........................................................
FR81 Family CCR Condition Code Register (CCR) .....................21, 23 CMP CMP (Compare Immediate Data and Destination Register) .............................................165 CMP (Compare Word Data in Source Register and Destination Register)............................167 CMP2 (Compare Immediate Data and Destination Register) .............................................169 Condition Code Register ANDCCR (And Condition Code Register and Immediate Data) ..................................
FR81 Family DMOV DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) ..........................................................187 DMOV (Move Word Data from Direct Address to Pre Decrement Register Indirect Address) ..........................................................191 DMOV (Move Word Data from Direct Address to Register) .............................................183 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) ...........
FR81 Family FBcc FBcc (Floating Point Conditional Branch)...........232 FBcc:D (Floating Point Conditional Branch with Delay Slot) ..................................234 FCMPs FCMPs (Single Precision Floating Point Compare) ..........................................................236 FDIVs FDIVs (Single Precision Floating Point Division) ..........................................................238 First One bit SRCH1 (Search First One bit position distance From MSB) ........................................
FR81 Family MULUH (Multiply Unsigned Halfword Data) ..........................................................352 ORH (Or Halfword Data of Source Register to Data in Memory) .........................................364 STH (Store Halfword Data in Register to Memory) ..........................................401, 403, 405 hazard Occurrence of register hazard...............................74 Register hazards .................................................
FR81 Family Mismatch in Acceptance and Cancellation of Interrupt ............................................................73 Non-maskable Interrupts (NMI) ...........................55 Pipeline Operation and Interrupt Processing ..........73 Points of Caution while using User Interrupts........66 Preparation while using user interrupts .................65 Processing during an Interrupt Processing Routine ............................................................66 RETI (Return from Interrupt)..........
FR81 Family MOV (Move Word Data in Program Status Register to Destination Register)............................338 MOV (Move Word Data in Source Register to Destination Register)............334, 336, 340 MOV (Move Word Data in Source Register to Program Status Register) ......................342 Move MOV (Move Word Data in Program Status Register to Destination Register)............................338 MOV (Move Word Data in Source Register to Destination Register)............
FR81 Family DMOVH (Move Halfword Data from Direct Address to Post Increment Register Indirect Address) ..........................................................207 DMOVH (Move Halfword Data from Post Increment Register Indirect Address to Direct Address) ..........................................................209 Prior Preparation Types of EIT Processing and Prior Preparation ............................................................43 Priority Levels Multiple EIT processing and Priority Levels .......
FR81 Family Slot Branching Instructions and Delay Slot ..................97 Software Interrupt INT (Software Interrupt) ...................................271 INTE (Software Interrupt for Emulator)..............273 Source Register ADD (Add Word Data of Source Register to Destination Register)............................107 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)...................111 ADDN (Add Word Data of Source Register to Destination Register)........................
FR81 Family SUBC SUBC (Subtract Word Data in Source Register and Carry bit from Destination Register) ..........................................................416 SUBN SUBN (Subtract Word Data in Source Register from Destination Register)............................418 Subroutine CALL (Call Subroutine)............................157, 159 CALL:D (Call Subroutine) ........................161, 163 RET (Return from Subroutine)...........................366 RET:D (Return from Subroutine) .......................
FR81 Family EOR (Exclusive Or Word Data of Source Register to Data in Memory) .................................213 EXTSB (Sign Extend from Byte Data to Word Data) ..........................................................221 EXTSH (Sign Extend from Byte Data to Word Data) ..........................................................223 EXTUB (Unsign Extend from Byte Data to Word Data) ..................................................225 EXTUH (Unsign Extend from Byte Data to Word Data) .......................
FR81 Family 474 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CM71-00105-1E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR81 Family 32-BIT MICROCONTROLLER PROGRAMMING MANUAL August 2009 the first edition Published FUJITSU MICROELECTRONICS LIMITED Edited Sales Promotion Dept.
