FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM26-00301-2E F2MC-8FX 8-BIT MICROCONTROLLER PROGRAMMING MANUAL
2 F MC-8FX 8-BIT MICROCONTROLLER PROGRAMMING MANUAL FUJITSU LIMITED
PREFACE ■ Purpose and Audience The F2MC-8FX is original 8-bit one-chip microcontrollers that support application specific IC (ASIC). It can be widely applied from household to industrial equipment starting with portable equipment. This manual is intended for engineers who actually develop products using the F2MC-8FX microcontrollers, especially for programmers who prepare programs using the assembly language for the F2MC-8FX series assembler. It describes various instructions for the F2MC8FX.
• • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information.
CONTENTS CHAPTER 1 1.1 1.2 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU ........... 1 Outline of F2MC-8FX CPU .................................................................................................................. 2 Configuration Example of Device Using F2MC-8FX CPU .................................................................. 3 CHAPTER 2 MEMORY SPACE ........................................................................................ 5 2.1 CPU Memory Space ...................
6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44 6.45 6.46 6.47 6.48 6.49 6.50 6.51 6.52 6.53 BBC (Branch if Bit is Clear) .............................................................................................................. 60 BBS (Branch if Bit is Set) .............................................................................................................
6.54 6.55 6.56 6.57 6.58 6.59 6.60 6.61 6.62 6.63 6.64 6.65 6.66 6.67 6.68 6.69 6.70 6.71 6.72 6.73 6.74 6.75 6.76 6.77 6.78 6.79 6.80 6.81 6.82 6.83 6.84 6.85 6.86 MOVW (MOVE Immediate Word Data to Extra Pointer) ................................................................ 154 MOVW (MOVE Word Data from Accumulator to Index Register) ................................................... 156 MOVW (MOVE Immediate Word Data to Index Register) ..............................................................
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Main changes in this edition Page Changes (For details, refer to main body.) 11 2.2.2 Program Area Table 2.2-2 CALLV Jump Address Table ( " FFC8H " → " FFC9H " ) 53 Execution example : ADDCW A ( NZVC = "1010" → NZVC = "0000" ) 147 Execution example : MOVW A, PC ( A = "F0 63" → A = "F0 62" ) ( PC = "F0 63" → PC = "F0 62" ) 176 6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory) ( " Transfer the word value from the memory indicated by SP to dr. Then, subtract 2 fromthe value of SP.
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CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU This chapter outlines the F2MC-8FX CPU and explains its configuration by example. 1.1 Outline of F2MC-8FX CPU 1.
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU 1.1 Outline of F2MC-8FX CPU The F2MC-8FX CPU is a high-performance 8-bit CPU designed for the embedded control of various industrial and OA equipment. ■ Outline of F2MC-8FX CPU The F2MC-8FX CPU is a high-performance 8-bit CPU designed for the control of various industrial and OA equipment. It is especially intended for applications requiring low voltages and low power consumption.
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU 1.2 Configuration Example of Device Using F2MC-8FX CPU The CPU, ROM, RAM and various resources for each F2MC-8FX device are designed in modules. The change in memory size and replacement of resources facilitate manufacturing of products for various applications. ■ Configuration Example of Device Using F2MC-8FX CPU Figure 1.2-1 shows a configuration example of a device using the F2MC-8FX CPU. Figure 1.
CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU 4
CHAPTER 2 MEMORY SPACE This chapter explains the F2MC-8FX CPU memory space. 2.1 CPU Memory Space 2.
CHAPTER 2 MEMORY SPACE 2.1 CPU Memory Space All of the data, program, and I/O areas managed by the F2MC-8FX CPU are assigned to the 64 Kbyte memory space of the F2MC-8FX CPU. The CPU can access each resource by indicating its address on the 16-bit address bus. ■ CPU Memory Space Figure 2.1-1 shows the address configuration of the F2MC-8FX memory space. The I/O area is located close to the least significant address, and the data area is arranged right above it.
CHAPTER 2 MEMORY SPACE 2.2 Memory Space and Addressing In addressing by the F2MC-8FX CPU, the applicable addressing mode related to memory access may change according to the address. Therefore, the use of the proper addressing mode increases the code efficiency of instructions. ■ Memory Space and Addressing The F2MC-8FX CPU has the following addressing modes related to memory access. ([ ] indicates one byte): • Direct addressing: Specify the lower 8 bits of the address using the operand.
CHAPTER 2 MEMORY SPACE Figure 2.
CHAPTER 2 MEMORY SPACE 2.2.1 Data Area The F2MC-8FX CPU data area can be divided into the following three for each purpose: • General-purpose register bank area • Stack area • Direct area ■ General-Purpose Register Bank Area The general-purpose register bank area in the F2MC-8FX CPU is assigned to 0100H to 01FFH. The generalpurpose register numbers are converted to the actual addresses according to the conversion rule shown in Figure 2.
CHAPTER 2 MEMORY SPACE Figure 2.2-3 Example of Saving Data in Stack Area Before execution MEMORY After execution MEMORY PUSHW A SP 1235H A ABCDH 67H 1235H 1234H SP 1233H A ABCDH 1233H 67H 1235H CDH 1234H ABH 1233H 1232H 1232H Figure 2.
CHAPTER 2 MEMORY SPACE 2.2.2 Program Area The program area in the F2MC-8FX CPU includes the following two: • Vector call instruction table • Reset and interrupt vector table ■ Vector Call Instruction Table FFC0H to FFCFH of the memory space is used as the vector call instruction table. The vector call instruction for the F2MC-8FX CPU provides access to this area according to the vector numbers included in the OP code and makes a subroutine call using the data written there as the jump address. Table 2.
CHAPTER 2 MEMORY SPACE Table 2.2-3 Reset and Interrupt Vector Table Interrupt No. Table address Upper data Reset Interrupt No.
CHAPTER 2 MEMORY SPACE 2.2.3 Arrangement of 16-bit Data in Memory Space The F2MC-8FX CPU can perform 16-bit data transfer and arithmetic operation though it is an 8-bit CPU. Arrangement of 16-bit data in the memory space is shown below. ■ Arrangement of 16-bit Data in Memory Space As shown in Figure 2.2-5, the F2MC-8FX CPU treats 16-bit data in the memory as upper data if it is written at the first location having a lower address and as lower data if it is written at the next location after that.
CHAPTER 2 MEMORY SPACE 14
CHAPTER 3 REGISTERS This chapter explains the F2MC-8FX dedicated registers and general-purpose registers. 3.1 F2MC-8FX Registers 3.2 Program Counter (PC) and Stack Pointer (SP) 3.3 Accumulator (A) and Temporary Accumulator (T) 3.4 Program Status (PS) 3.5 Index Register (IX) and Extra Pointer (EP) 3.6 Register Banks 3.
CHAPTER 3 REGISTERS 3.1 F2MC-8FX Registers In the F2MC-8FX series, there are two types of registers: dedicated registers in the CPU, and general-purpose registers in memory. ■ F2MC-8FX Dedicated Registers The dedicated register exists in the CPU as a dedicated hardware resource whose application is restricted to the CPU architecture. The dedicated register is composed of seven types of 16-bit registers. Some of these registers can be operated with only the lower 8 bits. Figure 3.
CHAPTER 3 REGISTERS 3.2 Program Counter (PC) and Stack Pointer (SP) The program counter (PC) and stack pointer (SP) are application-specific registers existing in the CPU. The program counter (PC) indicates the address of the location at which the instruction currently being executed is stored. The stack pointer (SP) holds the addresses of the data location to be referenced by the interrupt and stack push/pop instructions.
CHAPTER 3 REGISTERS 3.3 Accumulator (A) and Temporary Accumulator (T) The accumulator (A) and temporary accumulator (T) are application-specific registers existing in the CPU. The accumulator (A) is used as the area where the results of operations are temporarily stored. The temporary accumulator (T) is used as the area where the old data is temporarily saved for data transfer to the accumulator (A) or the operand for operations.
CHAPTER 3 REGISTERS Figure 3.3-3 Data Transfer between Accumulator (A) and Temporary Accumulator (T) (16-bit Transfer) Before execution After execution A 5678H A 1234H T XXXXH T 5678H MOVW A, #1234H Figure 3.3-4 Data Transfer between Accumulator (A) and Temporary Accumulator (T) (8-bit Transfer) After execution Before execution A 5678H A 5612H T XXXXH T MOV A, #12H XX78H Figure 3.
CHAPTER 3 REGISTERS 3.3.1 How To Use The Temporary Accumulator (T) The F2MC-8FX CPU has a special-purpose register called a temporary accumulator. This section described the operation of this register. ■ How to Use the Temporary Accumulator (T) The F2MC-8FX CPU has various binary operation instructions, some data transfer instructions and the temporary accumulator (T) for 16-bit data operation.
CHAPTER 3 REGISTERS 3.3.2 Byte Data Transfer and Operation of Accumulator (A) and Temporary Accumulator (T) When data transfer to the accumulator (A) is performed byte-by-byte, the transfer data is stored in the AL. Automatic data transfer to the temporary accumulator (T) is also performed byte-by-byte and only the contents of the original AL are stored in the TL. Neither the upper 8 bits of the accumulator nor the temporary accumulator are affected by the transfer.
CHAPTER 3 REGISTERS ■ Direct Data Transfer from Temporary Accumulator (T) The temporary accumulator (T) is basically temporary storage for the accumulator (A). Therefore, data from the temporary accumulator cannot be transferred directly to memory. However, as an exception, using the accumulator as a pointer enabling saving of the contents of the temporary accumulator in memory. An example of this case is shown below. Figure 3.
CHAPTER 3 REGISTERS 3.4 Program Status (PS) The program status (PS) is a 16-bit application-specific register existing in the CPU. In upper byte of program status (PS), the upper 5-bit is the register bank pointer (RP) and lower 3-bit is the direct bank pointer (DP). The lower byte of program status (PS) is the condition code register (CCR). The upper byte of program status (PS), i.e. RP and DP, is mapped to address 0078H.
CHAPTER 3 REGISTERS Table 3.4-1 Conversion Rule for Actual Address of Direct Addressing and Bit Direct Addressing Operand address Direct bank pointer (DP) 00H to 7FH Actual address 0000H to 007FH 80H to FFH 000 0080H to 00FFH 001 0100H to 017FH 010 0180H to 01FFH 011 0200H to 027FH 100 0280H to 02FFH 101 0300H to 037FH 110 0380H to 03FFH 111 0400H to 047FH ■ Program Status (PS) Flags The program status flags are explained below.
CHAPTER 3 REGISTERS This flag is 1 when a two’s complement overflow occurs and is 0 when one does not as the result of an operation. • C flag This flag is 1 when a carry or a borrow, from bit 7 in byte mode and from bit 15 in word mode, is generated as the result of an operation but 0 in other cases. The shifted-out value is provided by the shift instruction. ■ Access to Register Bank Pointer and Direct Bank Pointer The upper byte of program status (PS), i.e.
CHAPTER 3 REGISTERS 3.5 Index Register (IX) and Extra Pointer (EP) The index register (IX) and extra pointer (EP) are 16-bit application-specific registers existing in the CPU. The index register (IX) adds an 8-bit offset value with its sign to generate the address stored by the operand. The extra pointer (EP) indicates the address stored by the operand. ■ Index Register (IX) Figure 3.5-1 indicates the operation of the index register. Figure 3.
CHAPTER 3 REGISTERS 3.6 Register Banks The register bank register is an 8-bit general-purpose register existing in memory. There are eight registers per bank of which there can be 32 altogether. The current bank is indicated by the register bank pointer (RP). ■ Register Bank Register Figure 3.6-1 shows the configuration of the register bank. Figure 3.
CHAPTER 3 REGISTERS 3.7 Direct Banks The direct bank is in 0080H to 047FH of direct area, and composed of 128 bytes × 8 banks. The access that uses direct addressing and bit direct addressing in operand address 80H to FFH can be extended to 8 direct banks according to the value of the direct bank pointer (DP). The current bank is indicated by the direct bank pointer (DP). ■ Direct Bank Figure 3.7-1 shows the configuration of a direct bank.
CHAPTER 4 INTERRUPT PROCESSING This chapter explains the functions and operation of F2MC-8FX interrupt processing. 4.1 Outline of Interrupt Operation 4.2 Interrupt Enable/Disable and Interrupt Priority Functions 4.3 Creating an Interrupt Processing Program 4.4 Multiple Interrupt 4.
CHAPTER 4 INTERRUPT PROCESSING 4.1 Outline of Interrupt Operation F2MC-8FX series interrupts have the following features: • Four interrupt priority levels • All maskable features • Vector jump feature by which the program jumps to address mentioned in the interrupt vector. ■ Outline of Interrupt Operation In the F2MC-8FX series, interrupts are transferred and processed according to the following procedure: 1. An interrupt source occurs in resources. 2. Refer to interrupt enable bits in resources.
CHAPTER 4 INTERRUPT PROCESSING Figure 4.1-1 shows the flow diagram of F2MC-8FX interrupt operation. Internal bus Figure 4.
CHAPTER 4 INTERRUPT PROCESSING 4.2 Interrupt Enable/Disable and Interrupt Priority Functions In the F2MC-8FX series, interrupt requests are transferred to the CPU using the three types of enable/disable functions listed below.
CHAPTER 4 INTERRUPT PROCESSING Figure 4.2-1 Relationship between Interrupt Request and Interrupt Level in Resources To CPU Interrupt level register Resource #1 1H Interrupt request F/F 2H Resource #n 0H ... ... ... ...
CHAPTER 4 INTERRUPT PROCESSING 4.3 Creating an Interrupt Processing Program In the F2MC-8FX series, basically, interrupt requests from resources are issued by hardware and cleared by software. ■ Creating an Interrupt Processing Program The interrupt processing control flow is as follows: 1. Initialize resources before operation. 2. Wait until an interrupt occurs. 3. In the event of an interrupt, if the interrupt can be accepted, perform interrupt processing to branch to the interrupt processing routine.
CHAPTER 4 INTERRUPT PROCESSING Figure 4.3-2 Interrupt Response Time CPU operation Interrupt wait time Normal instruction execution Sample wait (a) Interrupt request issued Interrupt handling 9 instruction cycles (b) Interrupt processing program Indicates the last instruction cycle in which an interrupt is sampled. Note: It will take (a) + (b) instruction cycles to transfer control to the interrupt processing routine after an interrupt occurs.
CHAPTER 4 INTERRUPT PROCESSING 4.4 Multiple Interrupt The F2MC-8FX CPU can have a maximum of four levels as maskable interrupts. These can be used to assign priorities to interrupts from resources. ■ Multiple Interrupt A specific example is given below. • When giving priority over the A/D converter to the timer interrupt START MOV ADIL, #2 Set the interrupt level of the A/D converter to 2. MOV TMIL, #1 Set the interrupt level of the timer to 1.
CHAPTER 4 INTERRUPT PROCESSING 4.5 Reset Operation In the F2MC-8FX series, when a reset occurs, the flag of program status is 0 and the IL bit is set to 11. When cleared, the reset operation is executed from the starting address written to set vectors (FFFEH, FFFFH).
CHAPTER 4 INTERRUPT PROCESSING 38
CHAPTER 5 CPU SOFTWARE ARCHITECTURE This chapter explains the instructions for the F2MC-8FX CPU. 5.1 Types of Addressing Modes 5.
CHAPTER 5 CPU SOFTWARE ARCHITECTURE 5.
CHAPTER 5 CPU SOFTWARE ARCHITECTURE ■ Index Addressing (@IX+off) This addressing mode, indicated as "@IX+off" in the instruction list, is used to access the entire 64-Kbyte area. In this addressing mode, the contents of the first operand are sign-extended and then added to the index register (IX). The result is used as the address.
CHAPTER 5 CPU SOFTWARE ARCHITECTURE ■ Vector Addressing (#k) This addressing mode, indicated as "#k" in the instruction list, is used for branching to the subroutine address registered in the table. In this addressing mode, the information about #k is contained in the instruction code and the table addresses listed in Table 5.1-1 are created. Table 5.
CHAPTER 5 CPU SOFTWARE ARCHITECTURE 5.2 Special Instructions In the F2MC-8FX series, the following six special instructions are available: • JMP @A • MOVW A, PC • MULU A • DIVU A • XCHW A, PC • CALLV #k ■ JMP @A This instruction is used for branching to an address where the contents of the accumulator (A) are used. The contents of one of the N jump addresses arranged in table form is selected and transferred to the accumulator. Executing this instruction enables the N-branch processing.
CHAPTER 5 CPU SOFTWARE ARCHITECTURE ■ MULU A This instruction is used for multiplying 8 bits of the AL by 8 bits of the TL without a sign and stores the 16bit result in the accumulator (A). The contents of the temporary accumulator (T) do not change. In the operation, the original contents of the AH and TH are not used. Since the flag does not change, attention must be paid to the result of multiplication when branching accordingly.
CHAPTER 5 CPU SOFTWARE ARCHITECTURE Figure 5.2-1 Example of Using XCHW A, PC [Main routine] ... [Subroutine] MOVW A, #PUTSUB XCHW A, PC PUTSUB XCHW A, EP PUSHW A DB 'PUT OUT DATA', EOL PTS1 MOVW A, #1234H MOV A, @EP INCW EP ... MOV IO, A ... Output table data here. CMP A, #EOL BNE PTS1 POPW A XCHW A, EP JMP @A ■ CALLV #k This instruction is used for branching to a subroutine address registered in the table.
CHAPTER 5 CPU SOFTWARE ARCHITECTURE [Example] CALLV #3 Before execution PC 5678H SP 1234H (- 2) PC FEDCH SP 1232H DCH 1234H FEH FFC6H FEH ... FFC7H ... DCH ... 1234H ...
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS This chapter explains each execution instruction, used in the assembler, in reference format. All execution insurrections are described in alphabetical order. For information about the outline of each item and the meaning of symbols (abbreviations) explained for each execution instruction, see "CHAPTER 5 CPU SOFTWARE ARCHITECTURE".
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.1 ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to Accumulator) Add the byte data of TL to that of AL, add a carry to the LSB and then return the results to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ADDC A Memory FFFFH A 12 34 A 12 AC T 56 78 T 56 78 IX IX SP SP PC PC Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 1 0 1 0 (After execution) 49
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.2 ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator) Add the byte data of EA memory (memory expressed in each type of addressing) to that of AL, add a carry to the LSB and then return the results to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ADDC A, #25H Memory A 12 FFFFH 34 A T T IX IX SP SP PC PC Byte 12 Memory FFFFH Byte 0000H 5A 0000H EP EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 51
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.3 ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to Accumulator) Add the word data of T to that of A, add a carry to the LSB and then return the results to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ADDCW A Memory FFFFH A 12 34 A 68 AD T 56 78 T 56 78 IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 53
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.4 AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical AND on the byte data of AL and TL for every bit and return the result to AL. The byte data of AH is not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : AND A Memory FFFFH A 12 34 A 12 24 T XX 2C T XX 2C IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 55
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.5 AND (AND Byte Data of Accumulator and Memory to Accumulator) Carry out the logical AND on the byte data of AL and EA memory (memory expressed in each type of addressing) for every bit and return the result to AL. The byte data of AH is not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : AND , @EP Memory A 02 FFFFH 53 A T T IX IX 31 0123H SP SP PC PC EP Byte 01 PS Byte 0000H 23 Byte N Z V C 0 0 1 0 (Before execution) EP 02 01 FFFFH 31 0123H Byte 0000H 11 23 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 57
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.6 ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical AND on the word data of A and T for every bit and return the results to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ANDW A Memory FFFFH A 56 63 A 14 22 T 34 32 T 34 32 IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 59
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.7 BBC (Branch if Bit is Clear) Branch when the value of bit b in dir memory is 0. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BBC 84H : 0, 0FBH Memory FFFFH Memory FFFFH B0 E800H A A B0 E800H T T E7FEH IX IX SP SP bit0 bit0 PC E8 00 XXXX XXX0 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) PC E7 FE XXXX XXX0 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 1 0 0 (After execution) 61
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.8 BBS (Branch if Bit is Set) Branch when the value of bit b in dir memory is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BBS 84H : 0, 0FBH Memory FFFFH Memory FFFFH B0 E800H A A B0 E800H T T E7FEH IX IX SP SP bit0 bit0 PC E8 00 XXXX XXX1 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) PC E7 FE XXXX XXX1 0084H Byte EP PS 00 Byte Byte 0000H N Z V C 0 0 0 0 (After execution) 63
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.9 BC (Branch relative if C=1)/BLO (Branch if LOwer) Execute the next instruction if the C-flag is 0 and the branch if it is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BC 0FEH Memory FFFFH Memory A A T T IX IX FFFFH E804H F9 PC E8 PC Byte PS Byte Byte F9 F802H 02 EP FE SP FE SP 0000H N Z V C 1 1 1 0 (Before execution) E8 E802H 04 Byte EP PS Byte Byte 0000H N Z V C 1 1 1 0 (After execution) 65
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.10 BGE (Branch Great or Equal: relative if larger than or equal to Zero) Execute the next instruction if the logical exclusive-OR for the V and N flags is 1 and the branch if it is 0. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BGE 02H Memory FFFFH Memory A A T T IX IX FFFFH F458H FE PC F4 F456H PC 56 Byte EP PS Byte Byte 02 SP 02 SP 0000H N Z V C 0 1 1 1 (Before execution) F4 F456H Byte 0000H 58 EP PS Byte FE Byte N Z V C 0 1 1 1 (After execution) 67
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.11 BLT (Branch Less Than zero: relative if < Zero) Execute the next instruction if the logical exclusive-OR for the V and N flags is 0 and the branch if it is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BLT 02H Memory FFFFH Memory A A T T FFFFH F45AH IX IX F458H FF PC F4 F456H PC 56 Byte EP PS Byte Byte 02 SP 02 SP F458H 0000H N Z V C 0 1 1 1 (Before execution) F4 F456H Byte 0000H 5A EP PS Byte FF Byte N Z V C 0 1 1 1 (After execution) 69
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.12 BN (Branch relative if N = 1) Execute the next instruction if the N-flag is 0 and the branch if it is 1. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BN 02H Memory FFFFH Memory A A T T IX IX FC63H SP SP 02 02 PC FFFFH FC FB 5F FC5FH Byte EP PS Byte Byte 0000H N Z V C 1 1 1 0 (Before execution) PC FC 63 EP PS Byte Byte FB FC5FH Byte 0000H N Z V C 1 1 1 0 (After execution) 71
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.13 BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal) Execute the next instruction if the Z-flag is 1 and the branch if it is 0. Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BNZ 0FAH Memory FFFFH Memory A A T T IX IX FFFFH FE20H FC PC FE FE1EH PC 1E Byte EP PS Byte Byte FA SP FA SP 0000H N Z V C 0 1 0 0 (Before execution) FE FE1EH Byte 0000H 20 EP PS Byte FC Byte N Z V C 0 1 0 0 (After execution) 73
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.14 BNC (Branch relative if C = 0)/BHS (Branch if Higher or Same) Execute the next instruction if the C-flag is 1 and the branch if it is 0 . Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BNC 01H Memory FFFFH Memory A A T T IX IX FFFFH E805H E804H E804H F8 PC E8 E802H PC 02 Byte EP PS Byte Byte 01 SP 01 SP 0000H N Z V C 1 1 1 0 (Before execution) E8 E802H Byte 0000H 05 EP PS Byte F8 Byte N Z V C 1 1 1 0 (After execution) 75
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.15 BP (Branch relative if N = 0: PLUS) Execute the next instruction if the N-flag is 1 and the branch if it is 0 . Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BP 04H Memory FFFFH Memory A A T T IX IX FFFFH FC61H FA PC FC FC5FH PC 5F Byte EP PS Byte Byte 04 SP 04 SP 0000H N Z V C 1 0 1 1 (Before execution) FC FC5FH Byte 0000H 61 EP PS Byte FA Byte N Z V C 1 0 1 1 (After execution) 77
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.16 BZ (Branch relative if Z = 1)/BEQ (Branch if Equal) Execute the next instruction if the Z-flag is 0 and the branch if it is 1 . Branch address corresponds to the value of addition between the PC value (word value) of the next instruction and the value with rel code-extended (word value).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : BZ 0FAH Memory FFFFH Memory FFFFH A A FE20H T T FA FA FE1EH FD FE1EH FD IX IX SP SP FE1AH PC FE PC 1E Byte FE 1A 0000H Byte 0000H EP EP PS Byte Byte N Z V C 0 1 0 0 (Before execution) PS Byte Byte N Z V C 0 1 0 0 (After execution) 79
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.17 CALL (CALL subroutine) Branch to address of ext. Return to the instruction next to this one by using the RET instruction of the branch subroutine.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CALL 0FC00H Memory FFFFH Memory A A T T IX IX FFFFH 020AH 020AH SP PC 02 F6 SP OA PC 23 Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) 02 FC 26 08 0208H Byte 0000H 00 EP PS Byte F6 Byte N Z V C 0 0 0 0 (After execution) 81
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.18 CALLV (CALL Vectored subroutine) Branch to the vector address (VA) of vct. Return to the instruction next to this one by using the RET instruction of the branch subroutine. The vector address (VA) indicated by VCT is shown on the next page.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CALL #02H Memory FFFFH Memory FFFFH A A vct 00 FFC5H 02 EC FFC4H T T EC00H IX IX 0208H 0208H SP PC 02 E8 SP 08 PC 00 Byte EP PS Byte 0000H N Z V C 0 0 0 0 EC 01 06 PS Byte E8 0206H Byte 0000H 00 EP (Before execution) Byte 02 N Z V C 0 0 0 0 Byte (After execution) Table 6.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.19 CLRB (Clear direct Memory Bit) Set the contents of 1 bit (indicated by 3 lower bits (b) of mnemonic) of the direct area to 0.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CLRB 84H : 0 Memory FFFFH Memory A A T T IX IX SP SP 0000 000X 0084H 0000 0000 0084H PC PC 0000H Byte EP PS FFFFH 00 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 0000H Byte EP 00 Byte Byte N Z V C 0 0 0 0 (After execution) 85
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.20 CLRC (Clear Carry flag) Set the C-flag to 0. ■ CLRC (Clear Carry flag) Operation (C) ← 0 Assembler format CLRC Condition code (CCR) N Z V C - - - R +: Changed by executing instruction -: Not changed R: Set to 0 by executing instruction N: Not changed Z: Not changed V: Not changed C: Set to 0.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CLRC Memory FFFFH A A T T IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 87
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.21 CLRI (CLeaR Interrupt flag) Set the I-flag to 0.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CLRI Memory FFFFH A A T T IX IX SP SP PC PC 0000H Byte EP PS Byte H I 0 1 IL1 IL0 1 1 N Z V C 0 0 0 1 Byte (Before execution) Memory FFFFH Byte 0000H EP PS Byte H I 0 0 IL1 IL0 1 1 N Z V C 0 0 0 1 Byte (After execution) 89
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.22 CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator) Compare the byte data of AL with that of TL and set the results to CCR. AL and TL are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMP A Memory FFFFH A XX 75 A XX 75 T XX 48 T XX 48 IX IX SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 1 0 0 1 (After execution) 91
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.23 CMP (CoMPare Byte Data of Accumulator and Memory) Compare the byte data of AL with that of the EA memory (memory expressed in each type of addressing) and set the results to CCR. AL and EA memory are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMP A , 80H Memory A XX FFFFH A 23 T T IX IX 56 SP 0180H FFFFH 56 0180H Byte 0000H 23 SP PC PC Byte 0000H EP EP PS XX Memory 02 Byte Byte N Z V C 0 0 0 1 (Before execution) PS 02 Byte Byte N Z V C 1 0 0 1 (After execution) 93
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.24 CMP (CoMPare Byte Data of Immediate Data and Memory) Compare the byte data of EA memory (memory expressed in each type of addressing) with the immediate data and set the results to CCR. EA memory is not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMP @EP , #33H Memory FFFFH A A T T IX IX 54 SP 0120H FFFFH 54 0120H Byte 0000H SP PC PC EP Memory Byte 01 PS Byte 0000H 20 Byte N Z V C 0 0 0 1 (Before execution) EP 01 20 PS Byte Byte N Z V C 0 0 0 0 (After execution) 95
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.25 CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator) Compare the word data of A with that of T and set the results to CCR. A and T are not changed. ■ CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator) Operation (T) - (A) Assembler format CMPW A Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : CMPW A Memory FFFFH A 86 75 A 86 75 T 24 48 T 24 48 IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 1 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 1 0 1 1 (After execution) 97
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.26 DAA (Decimal Adjust for Addition) When adding the correction value to AL by the state in the carry before execution of instruction and half-carry, decimal operation is corrected. ■ DAA (Decimal Adjust for Addition) Operation (AL) ← (AL) + 6 or 60H or 66H (Add a correction value shown in the next page to AL and the value of AL according to the state of the C or H-flag.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DAA Memory A XX FFFFH A 4A XX T T IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 50 0000H EP EP H PS 0 I IL1 IL0 0 1 1 Byte N 0 Z V 0 0 C PS 0 H I 0 0 Byte Byte IL1 IL0 1 1 N Z V C 0 0 0 0 Byte (Before execution) (After execution) Table 6.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.27 DAS (Decimal Adjust for Subtraction) Subtract the correction value from AL according to the state of the C or H-flag before executing instruction. ■ DAS (Decimal Adjust for Subtraction) Operation (AL) ← (AL) - 6 or 60H or 66H (Subtract a correction value shown in the next page to AL and the value of AL according to the state of the C or H-flag.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DAS Memory A XX FFFFH A 2F XX T T IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 29 0000H EP EP H PS 1 I 0 IL1 IL0 1 Byte N 1 0 Z 0 V C 0 PS 0 H I 1 0 Byte Byte IL1 IL0 1 1 N Z V C 0 0 0 0 Byte (Before execution) (After execution) Table 6.27-1 Decimal Adjustment Table (DAS) C-flag H-flag Correction value C-flag after execution 0 1 0 1 0 1 1 0 00 66 06 60 0 1 0 1 Table 6.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.28 DEC (DECrement Byte Data of General-purpose Register) Decrement byte data of Ri by one. ■ DEC (DECrement Byte Data of General-purpose Register) Operation (Ri) ← (Ri) - 1 (byte subtract) Assembler format DEC Ri Condition code (CCR) N Z V C + + + - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DEC R2 Memory FFFFH Memory A A T T IX IX R2 R2 0112H FE SP 0112H FD SP R1 R1 R0 R0 0110H 0110H PC PC Byte Byte 0000H 0000H EP EP PS FFFFH 10 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 10 Byte Byte N Z V C 1 0 0 0 (After execution) 103
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.29 DECW (DECrement Word Data of Accumulator) Decrement word data of A by one. ■ DECW (DECrement Word Data of Accumulator) Operation (A) ← (A) - 1 (Word subtraction) Assembler format DECW A Condition code (CCR) N Z V C + + - - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW A Memory A 78 FFFFH 22 A T T IX IX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) 78 Memory FFFFH Byte 0000H 21 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 105
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.30 DECW (DECrement Word Data of Extra Pointer) Decrement word data of EP by one.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW EP Memory FFFFH A A T T IX IX SP SP PC PC EP 0000H Byte 12 34 PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP 12 FFFFH Byte 0000H 33 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 107
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.31 DECW (DECrement Word Data of Index Pointer) Decrement word data of IX by one.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW IX Memory FFFFH A A T T IX 16 IX 27 SP SP PC PC Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) 16 Memory FFFFH Byte 0000H 26 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 109
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.32 DECW (DECrement Word Data of Stack Pointer) Decrement word data of SP by one.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DECW SP Memory FFFFH Memory FFFFH Byte 0000H Byte 0000H N Z V C N Z V C 0 0 0 0 0 0 0 0 (Before execution) (After execution) 111
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.33 DIVU (DIVide Unsigned) Divide the word data of T by that of AL as an unsigned binary value. Return the quotient to A and the remainder to T. When A is 0, the result is indefinite and Z flag is 1 to show 0 division.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : DIVU A Memory FFFFH A 00 OA A 00 20 T 01 41 T 00 01 IX IX SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) Memory FFFFH Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 113
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.34 INC (INCrement Byte Data of General-purpose Register) Add 1 to byte data of Ri. ■ INC (INCrement Byte Data of General-purpose Register) Operation (Ri) ← (Ri) + 1 (Word addition) Assembler format INC Ri Condition code (CCR) N Z V C + + + - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of operation and set to 0 in other cases.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INC R1 Memory FFFFH A A T T IX IX SP SP R1 56 0108H Byte EP PS 08 Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) FFFFH 57 0109H R1 0109H R0 PC Memory R0 PC 0108H Byte EP PS 08 Byte Byte 0000H N Z V C 0 0 0 0 (After execution) 115
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.35 INCW (INCrement Word Data of Accumulator) Add 1 to word data of A. ■ INCW (INCrement Word Data of Accumulator) Operation (A) ← (A) +1 (Word addition) Assembler format INCW A Condition code (CCR) N Z V C + + - - +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB of A is 1 as the result of operation and set to 0 in other cases. Z: Set to 1 if the result of operation is 0000H and set to 0 in other cases.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW A Memory A 12 FFFFH A 33 T T IX IX SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) 12 Memory FFFFH Byte 0000H 34 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 117
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.36 INCW (INCrement Word Data of Extra Pointer) Add 1 to word data of EP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW EP Memory FFFFH A A T T IX IX SP SP PC PC EP 25 PS Byte Byte 0000H Byte 42 N Z V C 0 0 0 0 (Before execution) EP 25 FFFFH Byte 0000H 43 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 119
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.37 INCW (INCrement Word Data of Index Register) Add 1 to word data of IX.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW IX Memory FFFFH A A T T IX 25 IX 72 SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) 25 Memory FFFFH Byte 0000H 73 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 121
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.38 INCW (INCrement Word Data of Stack Pointer) Add 1 to word data of SP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : INCW SP Memory FFFFH A A T T IX IX SP FF SP FF 00 Memory FFFFH Byte 0000H 00 PC PC Byte 0000H EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 123
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.39 JMP (JuMP to address pointed by Accumulator) Transfer word data from A to PC.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : JMP @A Memory A F0 FFFFH A 89 T T IX IX SP SP PC XX PC XX Byte F0 89 F0 89 Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 1 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 125
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.40 JMP (JuMP to effective Address) Branch to the PC value indicated by ext.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : JMP 0E654H Memory FFFFH Memory A A T T IX IX FFFFH E654H 54 54 SP E6 SP 21 PC D8 D800H PC 00 Byte EP PS Byte Byte E6 0000H N Z V C 0 1 1 1 (Before execution) E6 D800H Byte 0000H 54 EP PS Byte 21 Byte N Z V C 0 1 1 1 (After execution) 127
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.41 MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by Accumulator) Transfer byte data from T to memory indirectly addressed by A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV @A, T Memory FFFFH A 01 20 A 01 20 T XX 3F T XX 3F Memory FFFFH 3F 0120H Byte 0000H IX IX XX SP 0120H SP PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 129
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.42 MOV (MOVE Byte Data from Memory to Accumulator) Transfer byte data from EA memory (memory expressed in each type of addressing) to A. Byte data in AL is transferred to TL. AH is not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV A, 83H Memory FFFFH A 11 22 A 11 51 T XX XX T XX 22 FFFFH 51 0383H Byte 0000H IX IX 51 0383H SP SP PC PC 0000H Byte EP EP PS Memory 06 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 06 Byte Byte N Z V C 0 0 0 0 (After execution) 131
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.43 MOV (MOVE Immediate Byte Data to Memory) Transfer byte immediate data to EA memory (memory expressed in each type of addressing). ■ MOV (MOVE Immediate Byte Data to Memory) Operation (EA) ← d8 (Byte transfer) Assembler format MOV EA, #d8 Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV @IX+02, #35H Memory FFFFH Memory A A T T IX 02 00 0202H XX IX 02 FFFFH 00 0202H 35 (IX+2) (IX+2) SP SP 0200H 0200H PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (After execution) 133
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.44 MOV (MOVE Byte Data from Accumulator to memory) Transfer bytes (data from AL) immediate data to EA memory (memory expressed in each type of addressing). ■ MOV (MOVE Byte Data from Accumulator to memory) Operation (EA) ← (AL) (Byte transfer) Assembler format MOV EA, A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOV 82H, A Memory A XX FFFFH A 06 T T IX IX SP SP FFFFH 06 0202H Byte 0000H 06 0202H XX PC PC Byte 0000H EP EP PS XX Memory 03 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 03 Byte Byte N Z V C 0 0 0 0 (After execution) 135
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.45 MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator) Transfer word data from T to memory indirectly addressed by A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW @A, T Memory FFFFH A 01 78 A 01 78 T FB AA T FB AA Memory FFFFH AA 0179H FB 0178H Byte 0000H IX IX XX SP 0179H 0178H XX SP PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 137
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.46 MOVW (MOVE Word Data from Memory to Accumulator) Transfer word data from EA and EA + 1 memories (EA is an address expressed in each type of addressing) to A. Word data in A is transferred to T.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, @IX+01H Memory FFFFH Memory A 01 02 A EF 23 T XX XX T 01 02 IX 01 50 IX 01 50 SP 23 23 EF EF SP FFFFH 0151H (IX+1) 0150H 0150H PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) Byte EP PS Byte Byte 0000H N Z V C 1 0 0 0 (After execution) 139
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.47 MOVW (MOVE Word Data from Extra Pointer to Accumulator) Transfer word data from EP to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, EP Memory A XX FFFFH A XX T T IX IX SP SP PC PC 96 Byte EP 32 PS Byte FFFFH Byte 0000H 32 0000H Byte EP 96 Memory N Z V C 0 0 0 0 (Before execution) 96 32 PS Byte Byte N Z V C 0 0 0 0 (After execution) 141
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.48 MOVW (MOVE Word Data from Index Register to Accumulator) Transfer word data from IX to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, IX Memory A XX FFFFH A XX 23 87 23 FFFFH Byte 0000H T T IX 87 Memory 87 IX 23 SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 143
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.49 MOVW (MOVE Word Data from Program Status Register to Accumulator) Transfer word data from PS to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, PS Memory A XX FFFFH A XX T T IX IX SP SP PC PC PS 0000H Byte EP 78 18 Byte Byte N Z V C 1 0 0 0 (Before execution) 78 Memory FFFFH Byte 0000H 18 EP PS 78 18 Byte Byte N Z V C 1 0 0 0 (After execution) 145
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.50 MOVW (MOVE Word Data from Program Counter to Accumulator) Transfer word data from PC to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, PC Memory A XX FFFFH A XX T T IX IX SP SP PC F0 PC 62 Byte F0 62 F0 62 Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 147
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.51 MOVW (MOVE Word Data from Stack Pointer to Accumulator) Transfer word data from SP to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW A, SP Memory A XX FFFFH A XX T T IX IX SP 69 SP 05 69 05 69 05 Memory FFFFH Byte 0000H PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 149
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.52 MOVW (MOVE Word Data from Accumulator to Memory) Transfer word data from A to EA and EA + 1 memories (memory expressed in each type of addressing). ■ MOVW (MOVE Word Data from Accumulator to Memory) Operation (EA) ← (A) (Word transfer) Assembler format MOVW EA, A Condition code (CCR) N Z V C - - - - +: Changed by executing instruction -: Not changed N: Not changed Z: Not changed V: Not changed C: Not changed Table 6.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW 93H, A Memory A 10 FFFFH A 56 T T IX IX XX 0094H XX 0093H SP FFFFH 56 0094H 10 0093H Byte 0000H 56 SP PC PC Byte EP PS 10 Memory 00 Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) EP PS 00 Byte Byte N Z V C 0 0 0 0 (After execution) 151
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.53 MOVW (MOVE Word Data from Accumulator to Extra Pointer) Transfer word data from A to EP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW EP, A Memory A 87 FFFFH A 65 T T IX IX SP SP PC PC XX Byte EP XX PS Byte 65 87 65 FFFFH Byte 0000H 0000H Byte EP 87 Memory N Z V C 1 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 153
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.54 MOVW (MOVE Immediate Word Data to Extra Pointer) Transfer word immediate data to EP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW EP, #2345H Memory FFFFH A A T T IX IX SP SP PC PC EP Byte XX PS Byte 0000H XX Byte N Z V C 0 0 0 0 (Before execution) EP 23 FFFFH Byte 0000H 45 PS Byte Memory Byte N Z V C 0 0 0 0 (After execution) 155
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.55 MOVW (MOVE Word Data from Accumulator to Index Register) Transfer word data from A to IX.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW IX, A Memory A 56 FFFFH 43 A 43 56 43 FFFFH Byte 0000H T T IX 56 Memory XX IX XX SP SP PC PC 0000H Byte EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 157
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.56 MOVW (MOVE Immediate Word Data to Index Register) Transfer word immediate data to IX.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW IX, #4567H Memory FFFFH A A T T IX XX IX XX SP SP PC PC Byte EP PS Byte Byte 0000H N Z V C 0 0 0 0 (Before execution) 45 Memory FFFFH Byte 0000H 67 EP PS Byte Byte N Z V C 0 0 0 0 (After execution) 159
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.57 MOVW (MOVE Word data from Accumulator to Program Status Register) Transfer word data from A to PS.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW PS, A Memory A 50 Memory FFFFH A 32 T T IX IX SP SP PC PC Byte 32 Byte 0000H 0000H EP EP PS 50 FFFFH XX XX Byte Byte N Z X X V X C X (Before execution) PS 50 32 Byte Byte N Z 0 0 V 1 C 0 (After execution) 161
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.58 MOVW (MOVE Immediate Word Data to Stack Pointer) Transfer word immediate data to SP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW SP, #6789H Memory FFFFH A A T T IX IX SP XX SP XX 67 Memory FFFFH Byte 0000H 89 PC PC 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 163
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.59 MOVW (MOVE Word data from Accumulator to Stack Pointer) Transfer word data from A to SP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MOVW SP, A Memory A 43 FFFFH A 21 T T IX IX SP XX SP XX 43 21 43 21 Memory FFFFH Byte 0000H PC PC 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 165
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.60 MULU (MULtiply Unsigned) Multiply the byte data of AL and TL as unsigned binary values. Return the results to the word data of A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : MULU A Memory FFFFH A XX 20 A 08 00 T XX 40 T XX 40 IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 167
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : NOP Memory FFFFH Memory A A T T FFFFH IX IX PC+1 PC+1 PC SP PC SP PC PC Byte 0000H EP N Z V Byte EP N C Z 0000H V C PS PS Byte Byte (Before execution) Byte Byte (After execution) 169
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.62 OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical OR on byte data of AL and TL for every bit and return the results to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : OR A Memory FFFFH A 15 23 A 15 63 T XX 41 T XX 41 IX IX SP SP PC PC Memory FFFFH Byte 0000H 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 171
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.63 OR (OR Byte Data of Accumulator and Memory to Accumulator) Carry out the logical OR on AL and EA memory (memory expressed in each type of addressing) for every bit and return the results to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : OR A, @EP Memory A 15 FFFFH Memory A 32 76 T T IX IX 56 0122H SP SP PC PC Byte EP 15 FFFFH 01 PS Byte 0000H EP 22 Byte N Z V C 0 0 0 0 (Before execution) 01 0122H Byte 0000H 22 PS Byte 56 Byte N Z V C 0 0 0 0 (After execution) 173
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.64 ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical OR on the word data of A and T for every bit and return the results to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ORW A Memory FFFFH A 57 23 A 77 63 T 33 41 T 33 41 IX IX SP SP PC PC Memory FFFFH Byte 0000H 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 175
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory) Subtract 2 from the value of SP. Then, transfer the word value from the memory indicated by SP to dr.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : PUSHW IX Memory FFFFH Memory A A T T IX 12 IX 34 12 FFFFH 34 0222H SP 02 22 0222H SP X 02 20 34 X 12 0220H Byte 0000H PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 177
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.66 POPW (POP Word Data of Intherent Register from Stack Memory) Transfer the word value from the memory indicated by SP to dr. Then, add 2 to the value of SP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : POPW A Memory A XX FFFFH Memory A XX T T IX IX 31 FFFFH 26 0235H SP 02 33 SP 26 02 35 26 0233H 31 31 0233H Byte 0000H PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 179
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.67 RET (RETurn from subroutine) Return the contents of PC saved in the stack. When this instruction is used in combination with the CALLV or CALL instruction, return to the next instruction to each of them.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : RET Memory FFFFH Memory A A T T IX IX SP 02 SP 06 02 0208H 08 10 PC F8 10 FC 09 FFFFH 0206H Byte PC FC 10 0000H FC 0206H Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 181
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.68 RETI (RETurn from Interrupt) Return the contents of PS and PC saved in the stack. Return PS and PC to the state before interrupt. ■ RETI (RETurn from Interrupt) Operation (PS) ← ((SP)), (PC) ← ((SP + 2)) (Word transfer) (SP) ← (SP) + 4 (Word addition) Assembler format RETI Condition code (CCR) N Z V C + + + + +: Changed by executing instruction -: Not changed N: Become to the saved value of N. Z: Become to the saved value of Z.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : RETI Memory FFFFH Memory A A T T IX IX FFFFH 020AH 10 10 SP 02 FC 06 SP 02 84 84 PC XX 0206H 08 XX Byte PC FC 10 0000H 08 0206H Byte 0000H EP EP PS 0208H FC OA XX XB Byte Byte N Z V C 1 0 1 1 (Before execution) PS 08 84 Byte Byte N Z V C 0 1 0 0 (After execution) 183
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.69 ROLC (Rotate Byte Data of Accumulator with Carry to Left) Shift byte data of AL with a carry one bit to the left. The contents of AH are not changed. ■ ROLC (Rotate Byte Data of Accumulator with Carry to Left) Operation AL C Assembler format ROLC A Condition code (CCR) N Z V C + + - + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of the shift and set to 0 in other cases.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : ROLC A Memory A XX FFFFH A 55 T T IX IX SP SP PC PC XX Memory FFFFH Byte 0000H AB 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 185
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.70 RORC (Rotate Byte Data of Accumulator with Carry to Right) Shift byte data of AL with a carry bit to the right. The contents of AH are not changed. ■ RORC (Rotate Byte Data of Accumulator with Carry to Right) Operation AL C Assembler format RORC A Condition code (CCR) N Z V C + + - + +: Changed by executing instruction -: Not changed N: Set to 1 if the MSB is 1 as the result of the shift and set to 0 in other cases.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : RORC A Memory A XX FFFFH A 55 T T IX IX SP SP PC PC XX Memory FFFFH Byte 0000H AA 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 1 (Before execution) PS Byte Byte N Z V C 1 0 0 1 (After execution) 187
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.71 SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to Accumulator) Subtract the byte data of AL from that of TL, subtract a carry and then return the result to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SUBC A Memory FFFFH A 12 23 A 12 11 T 76 34 T 76 34 IX IX SP SP PC PC Memory FFFFH Byte 0000H 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 189
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.72 SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator) Subtract the byte data of the EA memory (memory expressed in each type of addressing) from that of AL, subtract a carry and then return the results to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SUBC A, #37H Memory A 12 FFFFH A 34 T T IX IX SP SP PC PC 12 Memory FFFFH Byte 0000H FD 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 1 (After execution) 191
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.73 SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with Carry to Accumulator) Subtract the word data of A from that of T, subtract a carry and then return the result to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SUBCW A Memory FFFFH A 32 14 A 24 20 T 56 34 T 56 34 IX IX SP SP PC PC Memory FFFFH Byte 0000H 0000H Byte EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 193
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.74 SETB (Set Direct Memory Bit) Set the contents of 1 bit (indicated by 3 lower bits (b) of mnemonic) for the direct area to 1.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SETB 32H : 5 Memory Memory FFFFH A A T T IX IX 00X0 0000 0032H 0010 0000 0032H SP SP PC PC Byte 0000H Byte 0000H EP EP PS FFFFH 05 Byte Byte N Z V C 0 0 0 0 (Before execution) PS 05 Byte Byte N Z V C 0 0 0 0 (After execution) 195
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.75 SETC (SET Carry flag) Set the C-flag to 1.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SETC Memory FFFFH A A T T IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 1 (After execution) 197
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.76 SETI (SET Interrupt flag) Set the I-flag to 1 (enable an interrupt).
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SETI Memory FFFFH A A T T IX IX SP SP PC PC Byte 0000H EP H PS 0 Byte I 0 Byte IL1 IL0 1 1 N 0 Z 0 V 0 (Before execution) FFFFH Byte 0000H EP C 1 Memory PS Byte H I 0 1 Byte IL1 IL0 1 1 N Z V C 0 0 0 1 (After execution) 199
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.77 SWAP (SWAP Byte Data Accumulator "H" and Accumulator "L") Exchange the byte data of AH for that of AL.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : SWAP Memory A 32 FFFFH AA A T T IX IX SP SP PC PC Byte AA Memory FFFFH Byte 0000H 32 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 201
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.78 XCH (eXCHange Byte Data Accumulator "L" and Temporary Accumulator "L") Exchange the byte data of AL for that of TL.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCH A, T Memory FFFFH A 32 AA A 32 79 T 55 79 T 55 AA IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 203
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.79 XCHW (eXCHange Word Data Accumulator and Extrapointer) Exchange the word data of A for that of EP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, EP Memory A 32 FFFFH AA A T T IX IX SP SP PC PC Byte EP 55 Byte Byte 79 32 AA FFFFH Byte 0000H 0000H EP 79 PS 55 Memory N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 205
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.80 XCHW (eXCHange Word Data Accumulator and Index Register) Exchange the word data of A for that of IX.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, IX Memory A 32 FFFFH AA A 79 32 AA FFFFH Byte 0000H T T IX 55 Memory 55 IX 79 SP SP PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 207
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.81 XCHW (eXCHange Word Data Accumulator and Program Counter) Exchange the word data of PC for that of A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, PC Memory A F0 FFFFH C7 A T T IX IX SP SP PC F1 PC 79 Byte F1 7A F0 C7 Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 1 0 0 0 (Before execution) PS Byte Byte N Z V C 1 0 0 0 (After execution) 209
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.82 XCHW (eXCHange Word Data Accumulator and Stack Pointer) Exchange the word data of A for that of SP.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, SP Memory A 32 FFFFH AA A T T IX IX SP 55 SP 79 55 79 32 AA Memory FFFFH Byte 0000H PC PC Byte 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 211
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.83 XCHW (eXCHange Word Data Accumulator and Temporary Accumulator) Exchange the word data of A for that of T.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XCHW A, T Memory FFFFH A 32 AA A 55 79 T 55 79 T 32 AA IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 213
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.84 XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to Accumulator) Carry out the logical exclusive-OR on the byte data of AL and TL for every bit and return the results to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XOR A Memory FFFFH A 76 23 A 76 62 T XX 41 T XX 41 IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 215
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.85 XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator) Carry out the logical exclusive-OR for the byte data of AL and EA memory (memory expressed in each type of addressing) for every bit and return the results to AL. The contents of AH are not changed.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XOR A, @EP Memory A 54 Memory FFFFH 32 A 20 T T IX IX 12 0122H SP SP PC PC Byte EP 54 FFFFH 01 PS Byte 0000H EP 22 Byte N Z V C 0 0 0 0 (Before execution) 01 0122H Byte 0000H 22 PS Byte 12 Byte N Z V C 0 0 0 0 (After execution) 217
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 6.86 XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to Accmulator) Carry out the logical exclusive-OR on the word data of A and T for every bit and return the results to A.
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS Execution example : XORW A Memory FFFFH A 57 23 A 64 62 T 33 41 T 33 41 IX IX SP SP PC PC Byte Memory FFFFH Byte 0000H 0000H EP EP PS Byte Byte N Z V C 0 0 0 0 (Before execution) PS Byte Byte N Z V C 0 0 0 0 (After execution) 219
CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS 220
APPENDIX The appendix contains instruction and bus operation lists and an instruction map.
APPENDIX APPENDIX A Instruction List Appendix A contains lists of instructions used in the assembler. A.1 F2MC-8FX CPU Instruction Overview A.2 Operation List A.
APPENDIX A Instruction List A.1 F2MC-8FX CPU Instruction Overview This section explains the F2MC-8FX CPU instructions. ■ F2MC-8FX CPU Instruction Overview In the F2MC-8FX CPU, there is 140 kinds of one byte machine instruction (as the map, 256 bytes), and the instruction code is composed of the instruction and the operand following it. Figure A.1-1 shows the instruction code and the correspondence of the instruction map. Figure A.
APPENDIX ■ Sign of the Instruction List Table A.1-1 explains the sign used by describing the instruction code in the table. Table A.
APPENDIX A Instruction List ■ Item in Instruction Table Table A.1-2 explains the item of instruction table. Table A.1-2 Item in Instruction Table Item Description NMEMONIC The assembly description of the instruction is shown. RD The read of an internal bus is shown. WR The write of an internal bus is shown. RMW The read modification write signal of an internal bus is shown. ~ Cycle of the instruction number is shown. One instruction cycle is one machine cycle.
APPENDIX A.2 Operation List Table A.2-1 is the operation list for transfer instructions. Table A.2-2 is the operation list for operation instructions. Table A.2-3 is the operation list for branch instructions. Table A.2-4 is the operation list for other instructions. ■ Operation List Table A.
APPENDIX A Instruction List Table A.
APPENDIX Table A.
APPENDIX A Instruction List Table A.
APPENDIX Table A.
APPENDIX A Instruction List Table A.
APPENDIX Table A.
APPENDIX A Instruction List A.3 Flag Change Table Table A.3-1 is the flag change table for transfer instructions. Table A.3-2 is the flag change table for operation instructions. Table A.3-3 is the flag change table for branch instructions. Table A.3-4 is the flag change table for other instructions. ■ Flag Change Table Table A.
APPENDIX Table A.3-1 Flag Change Table (for Transfer Instructions) (2/2) Instruction Flag change MOVW A, EP N: Not changed MOVW EP, #d16 Z: Not changed MOVW IX, A V: Not changed MOVW A, IX C: Not changed MOVW SP, A MOVW A, SP MOVW SP, #d16 MOV @A, T N: Not changed MOVW @A, T Z: Not changed V: Not changed C: Not changed MOVW IX, #d16 N: Not changed MOVW A, PS Z: Not changed MOVW A, PC V: Not changed JMP @A C: Not changed MOVW PS, A N: Set to 1 if bit 3 of A is 1 and set to 0 if 0.
APPENDIX A Instruction List Table A.3-2 Flag Change Table (for Operation Instructions) (1/3) Instruction Flag change ADDC A, Ri N: Set to 1 if the result of operation is negative and set to 0 in other cases. ADDC A, #d8 Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. ADDC A, dir V: Set to 1 if an overflow occurs and set to 0 in other cases. ADDC A, @IX+off C: Set to 1 if a carry occurs and set to 0 in other cases.
APPENDIX Table A.3-2 Flag Change Table (for Operation Instructions) (2/3) Instruction Flag change DECW EP N: Not changed DECW IX Z: Not changed DECW SP V: Not changed C: Not changed DECW A N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.
APPENDIX A Instruction List Table A.3-2 Flag Change Table (for Operation Instructions) (3/3) Instruction XORW A Flag change N: Set to 1 if the result of operation is negative and set to 0 in other cases. Z: Set to 1 if the result of operation is 0 and set to 0 in other cases. V: Always set to 0 C: Not changed XOR A, #d8 N: Set to 1 if the result of operation is negative and set to 0 in other cases. XOR A, dir Z: Set to 1 if the result of operation is 0 and set to 0 in other cases.
APPENDIX Table A.3-3 Flag Change Table (for Branch Instructions) Instruction Flag change BZ rel/BEQ rel N: Not changed BNZ rel/BNE rel Z: Not changed BC rel/BLO rel V: Not changed BNC rel/BHS rel C: Not changed BN rel BP rel BLT rel BGE rel JMP addr16 N: Not changed Z: Not changed V: Not changed C: Not changed BBC dir:b, rel N: Not changed BBS dir:b, rel Z: Set to 1 if bit b is 0 and set to 0 if 1.
APPENDIX A Instruction List Table A.
APPENDIX APPENDIX B Bus Operation List Table B-1 is a bus operation list.
APPENDIX B Bus Operation List Table B-1 Bus Operation List (2/11) CODE MNEMONIC ~ Cycle Address bus 3 1 N +2 Data bus RD WR RMW The following instruction 1 0 0 05 MOV A, dir 15 CMP A, dir 2 dir address Data 1 0 0 25 ADDC A, dir 3 N +3 1 0 0 35 SUBC A, dir The following following instruction 55 XOR A, dir 65 AND A, dir 75 OR 45 MOV dir, A 1 N +2 The following instruction 1 0 0 2 dir address Data 0 1 0 3 N +3 The following following instruction 1 0
APPENDIX Table B-1 Bus Operation List (3/11) CODE MNEMONIC 08 - 0F MOV A, Ri 18 - 1F CMP A, Ri 28 - 2F ADDC A, Ri 38 - 3F SUBC A, Ri 58 - 5F XOR A, Ri 68 - 6F AND A, Ri 78 - 7F OR 48 - 4F MOV Ri, A 242 ~ Cycle 2 1 Address bus Data bus RD WR RMW N +2 The following following instruction 1 0 0 2 Rn address Data 1 0 0 1 N +2 The following following instruction 1 0 0 2 Rn address Data 0 1 0 1 1 N +2 The following following instruction 1 0 0 2 1 N +2 T
APPENDIX B Bus Operation List Table B-1 Bus Operation List (4/11) CODE F4 MNEMONIC XCHW A, PC A0 - A7 CLRB dir:n A8 - AF SETB dir:n B0 - B7 BBC dir:n, rel B8 - BF BBS dir:n, rel ~ Cycle 3 1 N +2 2 4 Address bus Data bus RD WR RMW Data of N +2 1 0 0 Address divergence The following instruction 1 0 0 3 Address divergence +1 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 1 2 dir address Data 1 0 1 3 dir address Data 0 1 0 4
APPENDIX Table B-1 Bus Operation List (5/11) CODE C4 D4 C5 D5 C6 D6 244 MNEMONIC MOVW A, ext MOVW ext, A MOVW A, dir MOVW dir, A MOVW A, @IX+off MOVW @IX+off, A ~ Cycle 5 1 N +2 2 5 4 4 4 4 Address bus Data bus RD WR RMW ext (L byte) 1 0 0 N +3 The following instruction 1 0 0 3 ext address Data (H byte) 1 0 0 4 ext+1 address Data (L byte) 1 0 0 5 N +4 The following following instruction 1 0 0 1 N +2 ext (L byte) 1 0 0 2 N +3 The following inst
APPENDIX B Bus Operation List Table B-1 Bus Operation List (6/11) CODE C7 D7 85 95 86 96 MNEMONIC ~ Cycle MOVW A, @EP 3 1 MOVW @EP, A MOV dir, #d8 CMP dir, #d8 MOV @IX+off, #d8 CMP @IX+off, #d8 3 4 4 4 4 Address bus Data bus RD WR RMW N +2 The following following instruction 1 0 0 2 (EP) address Data(H byte) 1 0 0 3 (EP)+1 address Data(L byte) 1 0 0 1 N +2 The following following instruction 1 0 0 2 (EP) address Data(H byte) 0 1 0 3 (EP)+1 address D
APPENDIX Table B-1 Bus Operation List (7/11) CODE 87 97 88 - 8F 98 - 9F 82 92 83 246 MNEMONIC ~ Cycle MOV @EP, #d8 3 1 N +2 2 CMP @EP, #d8 MOV Ri, #d8 CMP Ri, #d8 MOV @A, T MOV A, @A MOVW @A, T 3 3 3 2 2 3 Address bus Data bus RD WR RMW The following instruction 1 0 0 (EP) address Data 0 1 0 3 N +3 The following following instruction 1 0 0 1 N +2 The following instruction 1 0 0 2 (EP) address Data 1 0 0 3 N +3 The following following instruction
APPENDIX B Bus Operation List Table B-1 Bus Operation List (8/11) CODE 93 MNEMONIC MOVW A, @A ~ Cycle 3 1 Data bus RD WR RMW N +2 The following following instruction 1 0 0 2 (A) address Data (H byte) 1 0 0 3 (A) +1 address Data (L byte) 1 0 0 1 N +2 Data (L byte) 1 0 0 E4 MOVW A, #d16 E5 MOVW SP, #d16 2 N +3 The following instruction 1 0 0 E6 MOVW IX, #d16 3 N +4 The following following instruction 1 0 0 E7 MOVW EP, #d16 84 DAA 1 1 N +2 The followin
APPENDIX Table B-1 Bus Operation List (9/11) CODE F8 BNC rel F9 BC rel FA ~ Cycle Address bus Data bus RD WR RMW Divergence 1 N +2 Data of N +2 1 0 0 BP rel 2 N +3 Data of N +3 1 0 0 FB BN rel 3 Address divergence ahead The following instruction 1 0 0 FC BNZ rel 4 Address divergence ahead +1 The following following instruction 1 0 0 FD BZ rel FE BGE rel 1 N +2 The following instruction 1 0 0 FF BLT rel 2 N +3 The following following instruction 1 0
APPENDIX B Bus Operation List Table B-1 Bus Operation List (10/11) CODE 31 21 01 MNEMONIC CALL ext JMP ext MULU A ~ Cycle 6 1 4 8 Address bus Data bus RD WR RMW N +2 Address divergence ahead (L) 1 0 0 2 − − 0 0 0 3 SP -1 Return address (L) 0 1 0 4 SP -2 Return address (H) 0 1 0 5 Address divergence ahead The following instruction 1 0 0 6 Address divergence ahead +1 The following following instruction 1 0 0 1 N +2 Address divergence ahead (L) 1 0 0 2
APPENDIX Table B-1 Bus Operation List (11/11) CODE − MNEMONIC INTERRUPT ~ Cycle Address bus 9 1 N +2 2 Data bus RD WR RMW Data of N +2 1 0 0 Vector address Vector (H) 1 0 0 3 Vector address +1 Vector (L) 1 0 0 4 SP -1 Return address (L) 0 1 0 5 SP -2 Return address (H) 0 1 0 6 SP -3 PSL (CCR) 0 1 0 7 SP -4 PSH (RP, DP) 0 1 0 8 Address divergence ahead The following instruction 1 0 0 9 Address divergence ahead +1 The following following instruction
APPENDIX C Instruction Map APPENDIX C Instruction Map Table C-1 is an instruction map.
APPENDIX 252
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
INDEX Index Symbols A #imm Immediate Addressing (#imm) ............................ 41 #k Vector Addressing (#k)....................................... 42 @EP Pointer Addressing (@EP) .................................. 41 @IX+off Index Addressing (@IX+off)............................... 41 A Numerics 16-bit Data Arrangement of 16-bit Data in Memory Space ...... 13 Accumulator (A)................................................
INDEX BHS BNC (Branch relative if C=0)/BHS (Branch if Higher or Same) .............................................. 74 Bit Direct Addressing Bit Direct Addressing (dir:b)............................... 40 BLO BC (Branch relative if C=1)/BLO (Branch if LOwer) ............................................................ 64 BLT BLT (Branch Less Than zero: relative if < Zero) ............................................................ 68 BN BN (Branch relative if N=1)................................
INDEX ext Extended Addressing (ext) .................................. 40 Extended Addressing Extended Addressing (ext) .................................. 40 Extra Pointer Extra Pointer (EP) .............................................. 26 F Flag Program Status (PS) Flags................................... 24 Flag Change Flag Change Table ........................................... 233 G General-Purpose Register F2MC-8FX General-Purpose Registers.................
INDEX MOVW (MOVE Word Data from Program Counter to Accumulator)...................................... 146 MOVW (MOVE Word Data from Program Status Register to Accumulator) ..................... 144 MOVW (MOVE Word Data from Stack Pointer to Accumulator)...................................... 148 MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator)...................................... 136 MOVW A,PC ....................................................
INDEX SWAP SWAP (SWAP Byte Data Accumulator ’H’and Accumulator ’L’) ................................ 200 Vector Table Reset and Interrupt Vector Table ......................... 11 X T T Direct Data Transfer from Temporary Accumulator (T) ....................................................... 22 Example of Operation of Accumulator (A) and Temporary Accumulator (T) in Byte Data Processing ............................................ 21 How to Use the Temporary Accumulator (T) ........
CM26-00301-2E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-8FX 8-BIT MICROCONTROLLER PROGRAMMING MANUAL February 2008 the second edition Published FUJITSU LIMITED Edited Strategic Business Development Dept.
