C141-E202-01EN MHU2100AT DISK DRIVE PRODUCT MANUAL
FOR SAFE OPERATION Handling of This Manual This manual contains important information for using this product. Read thoroughly before using the product. Use this product only after thoroughly reading and understanding especially the section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.
Revision History (1/1) Edition Date 01 2004-01-20 Revised section (*1) (Added/Deleted/Altered) Details *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.
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Preface This manual describes MHU2100AT model of the MHU Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.
Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly.
Preface Attention Please forward any comments you may have regarding this manual. To make this manual easier for users to understand, opinions from readers are needed. Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet. Liability Exception “Disk drive defects” refers to defects that involve adjustment, repair, or replacement.
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Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly. Task Normal Operation Alert message Page Data corruption: Avoid mounting the disk near strong magnetic sources such as loud speakers.
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Manual Organization MHU2100AT DISK DRIVE PRODUCT MANUAL (C141-E202) • • • • • • Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHU2100AT • Maintenance and Diagnosis • Removal and Replacement Procedure DISK DRIVE MAINTENANCE MANUAL (C141-F067) C141-E202-01EN vii
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Contents CHAPTER 1 Device Overview........................................................................ 1-1 1.1 Features ..............................................................................................................1-2 1.1.1 Functions and performance .....................................................................1-2 1.1.2 Adaptability .............................................................................................1-2 1.1.3 Interface...................................
Contents CHAPTER 3 Installation Conditions ............................................................. 3-1 3.1 Dimensions ........................................................................................................ 3-2 3.2 Mounting............................................................................................................ 3-3 3.3 Cable Connections ............................................................................................. 3-9 3.3.1 Device connector ........
Contents 4.6.2 Write circuit.............................................................................................4-9 4.6.3 Read circuit............................................................................................4-10 4.6.4 Digital PLL circuit.................................................................................4-11 4.7 Servo Control ...................................................................................................4-12 4.7.1 Servo control circuit ...........
Contents (13) IDLE IMMEDIATE (X’95’ or X’E1’) .........................................5-36 (14) STANDBY (X’96’ or X’E2’) .......................................................5-37 (15) IDLE (X’97’ or X’E3’) .................................................................5-38 (16) CHECK POWER MODE (X’98’ or X’E5’) .................................5-40 (17) SLEEP (X’99’ or X’E6’) ..............................................................5-41 (18) SMART (X’B0) ...........................................
Contents (46) SET MAX ADDRESS EXT (X’37’): Option (customizing)............................................................................... 5-117 (47) WRITE MULTIPLE EXT (X’39’): Option (customizing)........ 5-119 (48) WRITE LOG EXT (X’3F’) [Optional command (Customize)] ................................................................................ 5-120 (49) READ VERIFY SECTOR (S) EXT (X’42): Option (customizing)...............................................................................
Contents 5.6.3.1 Initiating an Ultra DMA data in burst ..................................... 5-148 5.6.3.2 Ultra DMA data burst timing requirements ............................ 5-149 5.6.3.3 Sustained Ultra DMA data in burst ......................................... 5-152 5.6.3.4 Host pausing an Ultra DMA data in burst............................... 5-153 5.6.3.5 Device terminating an Ultra DMA data in burst ..................... 5-154 5.6.3.6 Host terminating an Ultra DMA data in burst.....................
Contents 6.4.3.1 Miss-hit ......................................................................................6-15 6.4.3.2 Sequential Hit.............................................................................6-16 6.4.3.3 Full hit ........................................................................................6-17 6.4.3.4 Partial hit ....................................................................................6-18 6.5 Write Cache.........................................................
Contents Illustrations Figures Figure 1.1 Figure 1.2 Negative voltage at +5 V when power is turned off ......................... 1-6 Current fluctuation (Typ.) at +5 V when power is turned on............................................................................................ 1-8 Figure 2.1 Figure 2.2 Figure 2.3 Disk drive outer view ........................................................................ 2-2 1 drive system configuration...........................................................
Contents Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 5.8 Figure 5.9 Figure 5.10 Figure 5.11 Figure 5.12 Figure 5.13 Figure 5.14 Figure 5.15 Figure 5.16 Figure 5.17 Figure 5.18 Figure 5.19 Figure 5.20 Figure 5.21 Execution example of READ MULTIPLE command .....................5-63 Read Sector(s) command protocol.................................................5-127 Protocol for command abort ..........................................................
Contents Tables Table 1.1 Table 1.2 Table 1.3 Table 1.4 Table 1.5 Table 1.6 Table 1.7 Specifications ................................................................................... 1-4 Examples of model names and product numbers.............................. 1-5 Current and power dissipation........................................................... 1-7 Environmental specifications ............................................................ 1-8 Acoustic noise specification............................
Contents Table 5.25 Relationship between combination of Identifier and Security level, and operation of the lock function ...........................5-92 Table 5.26 Contents of security password .......................................................5-100 Table 5.27 Command code and parameters ....................................................5-124 Table 5.28 Recommended series termination for Ultra DMA.........................5-145 Table 5.29 Ultra DMA data burst timing requirements .....................
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CHAPTER 1 Device Overview 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.9 Media Defects 1.10 Load/Unload Function 1.11 Advanced Power Management Overview and features are described in this chapter, and specifications and power requirement are described. The disk drive is 2.5-inch hard disk drives with built-in disk controllers.
Device Overview 1.1 Features 1.1.1 Functions and performance The following features of the disk drive is described. (1) Compact The disk drive has 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch). (2) Large capacity The disk drive can record up to 50 GB (formatted) on one disk using the RLL recording method and 30 recording zone technology. The disk drive has a formatted capacity of 100 GB (MHU2100AT).
1.1 Features 1.1.3 Interface (1) Connection to ATA interface The disk drive has built-in controllers compatible with the ATA interface. (2) Data buffer The disk drive use a 8MB data buffer to transfer data between the host and the disk media. In combination with the read-ahead cache system described in item (3) and the write cache described in item (7), the buffer contributes to efficient I/O processing.
Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives. Table 1.1 Specifications (1 of 2) MHU2100AT Format Capacity (*1) Number of Sectors (User) 100 GB 195,371,568 sector Bytes per Sector 512 bytes Rotational Speed 4,200 rpm ± 1% Average Latency 7.14 ms Positioning time (read and seek) • Minimum (Track-Track) • Average 1.5 ms (typ.) Read: 12ms (typ.) • Maximum (Full) 22 ms (typ.) Start time 3.5 sec (typ.
1.2 Device Specifications Table 1.1 lists the formatted capacity, number of logical cylinders, number of heads, and number of sectors of every model for which the CHS mode has been selected using the BIOS setup utility on the host. Table 1.1 Specifications (2 of 2) Model Capacity No. of Cylinder No. of Heads No. of Sectors MHU2100AT 8.45 GB 16,383 16 63 1.2.2 Model and product number Table 1.2 lists the model names and product numbers of the disk drive.
Device Overview 1.3 Power Requirements (1) Input Voltage • +5V ±5% (2) Ripple +5 V Maximum 100 mV (peak to peak) Frequency DC to 1 MHz (3) A negative voltage like the bottom figure isn't to occur at +5 V when power is turned off and, a thing with no ringing. Permissible level: −0.2 V 5 Voltage [V] 4 3 2 1 0 -1 0 100 200 300 400 500 600 700 800 Time [ms] Figure 1.
1.3 Power Requirements (4) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation (typical). Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) 0.9 A 4.5 W 130 mA 0.65 W Read 400 mA / Write 420mA Read 2.0 W / Write 2.1 W Seek (*5) 460 mA 2.3 W Standby 50 mA 0.25 W Sleep 20 mA 0.1 W — 0.007 W/GB (rank E) Spin up (*1) Idle R/W (on track) (*2) Energy Efficiency (*4) *1 Maximum current at starting spindle motor.
Device Overview (5) Current fluctuation (Typ.) at +5 V when power is turned on Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on (6) Power on/off sequence The voltage detector circuits monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence. 1.4 Environmental Specifications Table 1.4 lists the environmental specifications. Table 1.
1.5 Acoustic Noise 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item • Specification (typical) Idle mode (DRIVE READY) Sound Power 2.4B Sound Pressure (at 0.3m) 25.0dB Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification. Table 1.
Device Overview 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time Operating time Environment 250H/month or less 3000H/years or less 20 % or less of power-on time 5 to 55 °C/8 to 90 % But humidity bulb temperature 29 °C or less MTBF is defined as follows: Total operation time in all fields MTBF= (H) number of device failure in all fields (*1) *1 “Disk drive defects” refers to defects that involve repair, readjustment, or replacement.
1.8 Error Rate 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading 14 data of 10 bits.
Device Overview Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Normal Unload cannot be executed. Therefore, the number of Emergency other than Normal Unload is specified. Remark: We recommend cutting the power supply of the HDD for this device after the Head Unload operation completes.
1.11 Advanced Power Management Standby: The spindle motor stops. In APM Mode-1, which is the APM default mode, the operation status shifts till it finally reaches "Low Power Idle." Table 1.7 Advanced Power Management APM Mode Active Idle (VCM Lock) Low Power Idle (Unload) Standby (Spin Off) Mode-0 0.2-1.2 sec 15 min. N/A Mode-1 0.2-1.2 sec 10.0-40.0 sec N/A Mode-2 0.2-1.2 sec 10.0-40.0 sec 10.0-40.
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CHAPTER 2 Device Configuration 2.1 Device Configuration 2.2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate.
Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. Figure 2.1 Disk drive outer view (1) Disk The outer diameter of the disk is 65 mm. The inner diameter is 20 mm. (2) Head The heads are of the load/unload (L/UL) type.
2.2 System Configuration (6) Read/write circuit The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise. (7) Controller circuit The controller circuit consists of an LSI chip to improve reliability. The highspeed microprocessor unit (MPU) achieves a high-performance AT controller. 2.2 System Configuration 2.2.1 ATA interface Figures 2.2 and 2.3 show the ATA interface system configuration.
Device Configuration 2.2.3 2 drives connection (Host adaptor) MHC2032AT MHU2100AT MHC2040AT MHC2032AT MHU2100AT MHC2040AT Note: When the drive that is not conformed to ATA is connected to the disk drive above configuration, the operation is not guaranteed. Figure 2.3 2 drives configuration IMPORTANT HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-6 interface.
CHAPTER 3 Installation Conditions 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide.
Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.
3.2 Mounting 3.2 Mounting For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE (C141-E144)." (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. gravity (a) Horizontal –1 (b) Horizontal –1 gravity (d) Vertical –2 (c) Vertical –1 gravity (f) Vertical –4 (e) Vertical –3 Figure 3.
Installation Conditions (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 0.49N•m m (5kgf•cm). When attaching the HDD to the system frame, do not allow the system frame to touch parts (cover and base) other than parts to which the HDD is attached.
3.2 Mounting IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around φ 2.4 to block. Figure 3.
Installation Conditions (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 °C. Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling.
3.2 Mounting (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.6 Service area Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields. Damage: Do not press the cover of the disk drive.
Installation Conditions - General notes ESD mat Shock absorbing mat Wrist strap Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically to avoid falling down. Do not drop. Figure 3.7 Handling cautions - Installation (1) Please use the driver of a low impact when you use an electric driver. HDD is occasionally damaged by the impact of the driver.
3.3 Cable Connections 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. Connector, setting pins PCA Figure 3.
Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications ATA interface and power supply cable (44-pin type) Name Model Manufacturer Cable socket (44-pin type) 89361-144 FCI IMPORTANT For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.
3.4 Jumper Settings 3.3.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). Figure 3.10 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.11 shows the location of the jumpers to select drive configuration and functions. Figure 3.
Installation Conditions 3.4.2 Factory default setting Figure 3.12 shows the default setting position at the factory. Open Figure 3.12 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. 1 Open A C 1 C A Short Open 2 D B 2 D B Open (a) Master drive (b) Slave drive Figure 3.13 Jumper setting of master or slave drive Note: Pins A and C should be open.
3.4 Jumper Settings 3.4.4 CSEL setting Figure 3.14 shows the cable select (CSEL) setting. Open 1 C A 2 D B Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.14 CSEL setting Figure 3.15 and 3.16 show examples of cable selection using unique interface cables. By connecting the CSEL of the master drive to the CSEL Line (conducer) of the cable and connecting it to ground further, the CSEL is set to low level. The drive is identified as a master drive.
Installation Conditions drive drive Figure 3.16 Example (2) of Cable Select 3.4.5 Power Up in Standby setting When pin C is grounded, the drive does not spin up at power on.
CHAPTER 4 Theory of Device Operation 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on Sequence 4.5 Self-calibration 4.6 Read/write Circuit 4.7 Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.
Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA). The DE contains all movable parts in the disk drive, including the disk, spindle, actuator, read/write head, and air filter.
4.3 Circuit Configuration 4.2.4 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE. The circulation filter cleans out dust and dirt from inside the DE.
Theory of Device Operation (4) Controller circuit Major functions are listed below. • ATA interface control and data transfer control • Data buffer management • Sector format control • Defect management • ECC control • Error recovery and self-diagnosis Figure 4.
4.3 Circuit Configuration ATA Interface PCA Console MCU & HDC & RDC (88i5531; Marvell) Data Buffer SDRAM MCU HDC Flash ROM FROM RDC SVC TLS2255 Shock Sensor Resonator 20MHz DE SP Motor VCM Thermistor R/W Pre-Amp Media HEAD TLS26B624 Figure 4.
Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor. b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to the ATA bus.
4.5 Self-calibration 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations. 4.5.1 Self-calibration contents (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned.
Theory of Device Operation 4.5.2 Execution timing of self-calibration Self-calibration is performed once when power is turned on. After that, the disk drive does not perform self-calibration until it detects an error. That is, self-calibration is performed each time one of the following events occur: • When it passes from the power on for about 7 or 8 seconds except that the disk drive shifts to Low Power Idle mode, Standby mode and Sleep mode by execution of any commands.
4.6 Read/write Circuit 4.6 Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit. 4.6.1 Read/write preamplifier (PreAMP) PreAMP equips a read preamplifier and a write current switch, that sets the bias current to the MR device and the current in writing.
Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the ENDEC circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.
4.6 Read/write Circuit (3) FIR circuit This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) A/D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data. (5) Viterbi detection circuit The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit.
Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand. 4.7.1 Servo control circuit Figure 4.6 is the block diagram of the servo control circuit.
4.7 Servo Control (1) Microprocessor unit (MPU) The MPU executes startup of the spindle motor, movement to the reference cylinder, seek to the specified cylinder, and calibration operations. Main internal operation of the MPU are shown below. The major internal operations are listed below. a. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area.
Theory of Device Operation (5) Spindle motor control circuit The spindle motor control circuit controls the sensor-less spindle motor. A spindle driver IC with a built-in PLL(FLL) circuit that is on a hardware unit controls the sensor-less spindle motor. (6) Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor.
4.7 Servo Control 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving. (2) Data area This area is used as the user data area SA area.
Theory of Device Operation Servo frame (160 servo frames per revolution) IGB OGB Data area expand CYLn CYLn + 1 CYLn – 1 (n: even number) Diameter direction W/R Recovery Servo Mark Gray Code W/R Recovery Servo Mark Gray Code W/R Recovery Servo Mark Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase Circumference Direction Erase: DC erase area PAD Figure 4.
4.7 Servo Control 4.7.3 Servo frame format As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code, servo A to D, and PAD. Figure 4.8 shows the servo frame format. Figure 4.
Theory of Device Operation 4.7.4 Actuator motor control The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive current.
4.7 Servo Control 4.7.5 Spindle motor control Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3phase full/half-wave analog current control circuit is used as the spindle motor driver (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
Theory of Device Operation pump for 0.714 ms × k (k: constant value). This makes the flowed current into the motor higher and the rotational speed up. When the actual rotational speed is faster than 4,200 rpm, the MPU discharges the pump the other way. This control (charging/discharging) is performed every 1 revolution.
CHAPTER 5 Interface 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing This chapter gives details about the interface, and the interface commands and timings.
Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals.
5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No.
Interface [signal] ENCSEL [I/O] I [Description] This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- I MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting Pin A, B Short: Slave setting PUS- I When pin C is grounded, the drive does not spin up at power on. RESET- I Reset signal from the host.
5.1 Physical Interface [signal] [I/O] [Description] CS0- I Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- I Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers. DA 0-2 I Binary decoded address signals asserted by the host to access task file registers.
Interface [signal] DMARQ [I/O] [Description] O This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals. This signal hand shakes with the DMACK-signal.
5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through inputoutput (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers. Table 5.
Interface Device/Head, Cylinder High, Cylinder Low, Sector Number registers indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively. If the LBA mode is specified with 48-bit address information, the Cylinder High, Cylinder Low, Sector Number registers are set twice. In the first time, the registers indicate LBA bits 47 to 40, bits 39 to 32, and bits 31 to 24, respectively.
5.2 Logical Interface - Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution. - Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not Found error occurred. [Diagnostic code] X’01’: No Error Detected. X’02’: HDC Diagnostic Error X’03’: Data Buffer Diagnostic Error. X’04’: Memory Diagnostic Error. X’05’: Reading the system area is abnormal. X’06’: Calibration is abnormal. X’80’: Device 1 (slave device) Failed.
Interface (5) Sector Number register (X’1F3’) The contents of this register indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command. Under the LBA mode, this register indicates LBA bits 7 to 0. Under the LBA mode of the EXT system command, LBA bits 31 to 24 are set in the first setting, and LBA bits 7 to 0 are set in the second setting.
5.2 Logical Interface (8) Device/Head register (X’1F6’) The contents of this register indicate the device and the head number. When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X L X DEV HS3 HS2 HS1 HS0 - Bit 7: Unused - Bit 6: L. 0 for CHS mode and 1 for LBA mode. - Bit 5: Unused - Bit 4: DEV bit.
Interface - Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers. If the host system reads any command block register when BSY bit is 1, the contents of the Status register are posted.
5.2 Logical Interface (10) Command register (X’1F7’) The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately. Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written. 5.2.
Interface (2) Device Control register (X’3F6’) The Device Control register contains device interrupt and software reset. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HOB X X X X SRST nIEN 0 - Bit 7: High Order Byte (HOB) is the selector bit that selects higher-order information or lower-order information of the EXT system command. If HOB = 1, LBA bits 47 to 24 and the higher-order 8 bits of the sector count are displayed in the task register.
5.3 Host Commands Table 5.
Interface Table 5.
5.3 Host Commands Notes: FR: Features Register CY: Cylinder Registers SC: Sector Count Register DH: Drive/Head Register SN: Sector Number Register R: Retry at error 1 = Without retry 0 = With retry Y: Necessary to set parameters Y*: Necessary to set parameters under the LBA mode. N: Not necessary to set parameters (The parameter is ignored if it is set.) N*: May set parameters D: The device parameter is valid, and the head parameter is ignored.
Interface 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection. Example: READ SECTOR(S) At command issuance (I/O registers setting contents) Bit 7 6 5 4 3 2 1 0 1F7H(CM) 0 0 1 0 0 0 0 0 1F6H(DH) x L x DV Head No.
5.3 Host Commands SC: Sector Count register x, xx: Do not care (no necessary to set) Note: 1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most significant bit) and bits of the SN register are the LSB (least significant bit). 2. At error occurrence, the SC register indicates the remaining sector count of data transfer. 3.
Interface (1) RECALIBRATE (X’10’ to X’1F’) This command performs the calibration. Upon receipt of this command, the device sets BSY bit of the Status register and performs a calibration. When the device completes the calibration, the device updates the Status register, clears the BSY bit, and generates an interrupt. This command can be issued in the LBA mode.
5.3 Host Commands (2) READ SECTOR(S) (X’20’ or X’21’) This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be specified from 1 to 256 sectors. To specify 256 sectors reading, ‘00’ is specified. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.
Interface (R: Retry) At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No. [LSB] / LBA 1F3H(SN) End sector No. / LBA [LSB] 1F2H(SC) 00 (*1) 1F1H(ER) Error information *1 5-22 Status information If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
5.3 Host Commands (3) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command. The READ LONG command supports only single sector operation.
Interface (4) WRITE SECTOR(S) (X’30’ or X’31’) This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified from 1 to 256 sectors. A sector count of 0 requests 256 sectors. Data transfer begins at the sector specified in the Sector Number register. For the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.
5.3 Host Commands At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No. [LSB] / LBA 1F3H(SN) End sector No. / LBA [LSB] 1F2H(SC) 00 (*1) 1F1H(ER) Error information *1 C141-E202-01EN L x DV End head No. / LBA [MSB] If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
Interface (5) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation. The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET FEATURES command.
5.3 Host Commands (6) WRITE VERIFY (X’3C’) This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sector immediately after being written. The verify operation is a read and check for data errors without data transfer. Any error that is detected during the verify operation is posted. After all sectors are verified, the last interruption (INTRQ for command termination) is generated.
Interface (7) READ VERIFY SECTOR(S) (X’40’ or X’41’) This command operates similarly to the READ SECTOR(S) command except that the data is not transferred to the host system. After all requested sectors are verified, the device clears the BSY bit of the Status register and generates an interrupt. Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector number of the last sector verified.
5.3 Host Commands (8) SEEK (X’70’ to X’7F’) This command performs a seek operation to the track and selects the head specified in the command block registers. After completing the seek operation, the device clears the BSY bit in the Status register and generates an interrupt. In the LBA mode, this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address.
Interface (9) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device. This command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If two devices are present, both devices execute self-diagnosis. If device 1 is present: • Both devices shall execute self-diagnosis. • The device 0 waits for up to 6 seconds until device 1 asserts the PDIAGsignal.
5.3 Host Commands attention: The device responds to this command with the result of power-on diagnostic test. At command issuance (I/O registers setting contents) 1F7H(CM) 1 0 0 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) xx 0 0 0 0 Head No.
Interface (10) INITIALIZE DEVICE PARAMETERS (X’91’) The host system can set the number of sectors per track and the maximum head number (maximum head number is “number of heads minus 1”) per cylinder with this command. Upon receipt of this command, the device sets the BSY bit of Status register and saves the parameters. Then the device clears the BSY bit and generates an interrupt. When the SC register is specified to X’00’, an ABORTED COMMAND error is posted.
5.
Interface Table 5.5 Operation of DOWNLOAD MICRO CODE Host Command Subcommand code (FR Reg) 01h 07h Excluding 01h and 07h Movement of device Sector count (SN, SC Reg) Data transfer Microcode rewriting execution 0000h Non Rewriting execution reservation xxxxh It is. Rewriting execution reservation 0000h Non Execution. ** xxxxh It is. Execution. ** − Abort **: In the following cases, Subcommand code=07h returns Abort as an error though becomes Microcode rewriting execution specification.
5.3 Host Commands (12) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the APS timer function.
Interface (13) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the APS timer function.
5.3 Host Commands (14) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. If the device has already spun down, the spin-down sequence is not implemented. By using this command, the APS (Automatic Power Standby) timer function is enabled and the timer starts the countdown when the device returns to the state which is waiting Host Command.
Interface (15) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented.
5.
Interface (16) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by the contents of the Sector Count register. The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt.
5.3 Host Commands (17) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the sleep mode. In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive.
Interface (18) SMART (X’B0) This command predicts the occurrence of device failures depending on the subcommand specified in the FR register. If the FR register contains values that are not supported with the command, the Aborted Command error is issued. Before issuing the command, the host must set the key values in the CL and CH registers (4Fh in the CL register and C2h in the CH register). If the key values are incorrect, the Aborted Command error is issued.
5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister X’D0’ X’D1’ X’D2’ Function SMART READ DATE: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host. * For information about the format of the attribute value information, see Table 5.8.
Interface Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister X’D5’ Function SMART READ LOG: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer. SN: 00h: 01h: 02h: 06h: 09h: 80h-9Fh: X’D6’ SC: 01h: 01h: 33h: 01h: 01h: 01h-10h: * See Table 5.16 concerning the SMART error log data format. See Table 5.
5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister X’DA’ X’DB’ Function SMART RETURN STATUS: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values. If there is an attribute value exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers.
Interface At command issuance (I-O registers setting contents) 1F7H(CM) 1 0 1 1 1F6H(DH) x x x DV 1F5H(CH) Key (C2h) 1F4H(CL) Key (4Fh) 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) Subcommand 0 0 0 0 xx At command completion (I-O registers setting contents) 1F7H(ST) 1F6H(DH) Status information x x x DV xx 1F5H(CH) Key-failure prediction status (C2h/2Ch) 1F4H(CL) Key-failure prediction status (4Fh/F4h) 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information The attribute value inform
5.3 Host Commands Table 5.8 Format of device attribute value data Byte 00 01 02 03 04 05 06 07 to 0C 0D 0E to 169 16A 16B 16C, 16D 16E 16F 170, 171 172 173 174 175 176 177 to 181 182 to 1FE 1FF Item Data format version number Attribute 1 Attribute ID Status flag Current attribute value Attribute value for worst case so far Raw attribute value Reserved Attribute 2 to (The format of each attribute value is the same as attribute 30 that of bytes 02 to 0D.
Interface • Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same. When a data format is changed, the data format version numbers are updated. • Attribute ID The attribute ID is defined as follows: Attribute ID 5-48 Attribute name 0 (Indicates unused attribute data.
5.3 Host Commands • Status Flag Bit Meaning 0 If this bit is 1, it indicates normal operations are assured with the attribute when the attribute value exceeds the threshold value. 1 If this bit is 1 (0), it indicates the attribute only updated by an online test (off-line test). 2 If this bit 1, it indicates the attribute that represents performance. 3 If this bit 1, it indicates the attribute that represents an error rate.
Interface Table 5.10 Off-line data collection status Status Byte 00h or 80h 02h or 82h 04h or 84h 05h or 85h 06h or 86h 40 to 7Fh C0h to FFh 01h or 81h 03h or 83h 07h or 3Fh 87h to BFh • Meaning Off-line data acquisition is not executed. Off-line data acquisition has ended without an error. Off-line data acquisition is interrupted by a command from the host. Off-line data acquisition has ended before completion because of a command from the host.
5.3 Host Commands • Off-line data collection capability Indicates the method of off-line data collection carried out by the drive. If the offline data collection capability is 0, it indicates that off-line data collection is not supported. Table 5.12 Off-line data collection capability • Bit Meaning 0 If this bit is 1, it indicates that the SMART EXECUTE OFFLINE IMMEDATE sub-command (FR register = D4h) is supported.
Interface • Error logging capability Table 5.14 Error logging capability Bit Meaning 0 If this bit is 1, it indicates that the drive error logging function is supported. 1 to 7 • Reserved bits Check sum Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time from the beginning. • Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. Table 5.
5.3 Host Commands • SMART error logging If the device detects an unrecoverable error during execution of a command received from the host, the device registers the error information in the SMART Summary Error Log (see Table 5.16) and the SMART Comprehensive Error Log (see Table 5.17), and saves the information on media. The host issues the SMART Read Log Sector sub-command (FR register = D5h, SN register = 01h, SC register = 01h) and can read the SMART Summary Error Log.
Interface Table 5.
5.3 Host Commands • Command data structure Indicates the command received when an error occurs. • Error data structure Indicates the status register when an error occurs. • Total number of drive errors Indicates total number of errors registered in the error log. • Check sum Two's complementary for the lowest-order 1 byte that is obtained by adding 1 byte after another for as many as 511 bytes beginning from the top of the structure.
Interface • SMART Self-Test The host computer can issue the SMART Execute Off-line Immediate subcommand (FR Register = D4h) and cause the device to execute a self-test. When the self-test is completed, the device saves the SMART self-test log to the disk medium. The host computer can issue the SMART Read Log Sector sub-command (FR Register = D5h, SN Register = 06h, SC register = 01h) and can read the SMART self-test log. Table 5.
5.3 Host Commands Table 5.19 Selective self-test log data structure Offset 00h, 01h Description Data Structure Revision Number 02h...09h Test Span 1 0Ah...11h 12h...19h Test Span 2 1Ah...21h 22h...29h Test Span 3 2Ah...31h 32h...39h Test Span 4 3Ah...41h 42h...49h Test Span 5 4Ah...51h 52h...151h Initial 01h, 00h Starting LBA 00h...00h Ending LBA 00h...00h Starting LBA 00h...00h Ending LBA 00h...00h Starting LBA 00h...00h Ending LBA 00h...00h Starting LBA 00h...
Interface • Feature Flags Table 5.20 Selective self-test feature flags Bit Description 0 Vendor specific (unused) 1 When set to one, perform off-line scan after selective test 2 Vendor specific (unused) 3 When set to one, off-line scan after selective test is pending. 4 When set to one, off-line scan after selective test is active. 5...15 Reserved Bit [l] shall be written by the host and returned unmodified by the device.
5.3 Host Commands (19) DEVICE CONFIGURATION (X'B1') Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register. The following table shows these Features register values. If this command sets with the reserved value of Features register, an aborted error is posted.
Interface • DEVICE CONFIGURATION RESTORE (FR = C0h) The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command. After execution of this command, the settings are kept for the device power down or reset.
5.3 Host Commands bit. After execution of this command, the settings are kept for the device power down or reset. If the restriction of Multiword DMA modes or Ultra DMA modes is executed, a SET FEATURES command should be issued for the modes restriction prior the DEVICE CONFIGURATION SET command is issued. When the Automatic Acoustic Management function is assumed to be a unsupport, Automatic Acoustic Management is prohibited beforehand by SET FEATURES command (FR=C2h).
Interface Table 5.21 DEVICE CONFIGURATION IDENTIFY data structure Word Value Content 0 X'0001' Data structure revision 1 X'0007' Multiword DMA modes supported Reflected in IDENTIFY information "WORD63". Bit 15-3: Reserved 2 X'003F' Bit 2: 1 = Multiword DMA mode 2 and below are supported Bit 1: 1 = Multiword DMA mode 1 and below are supported Bit 0: 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported Reflected in IDENTIFY information "WORD88".
5.3 Host Commands (20) READ MULTIPLE (X’C4’) The READ MULTIPLE Command performs the same as the READ SECTOR(S) Command except that when the device is ready to transfer data for a block of sectors, and enters the interrupt pending state only before the data transfer for the first sector of the block sectors. In the READ MULTIPLE command operation, the DRQ bit of the Status register is set only at the start of the data block, and is not set on each sector.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 1F6H(DH) x L x DV 0 1 0 0 Start head No. / LBA [MSB] 1F5H(CH) Start cylinder No. [MSB] / LBA 1F4H(CL) Start cylinder No. [LSB] / LBA 1F3H(SN) Start sector No. / LBA [LSB] 1F2H(SC) Transfer sector count 1F1H(FR) xx At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No.
5.3 Host Commands (21) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command. The DRQ bit of the Status register is required to set only at the start of the data block, not on each sector.
Interface At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 5-66 Status information x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No. [LSB] / LBA 1F3H(SN) End sector No.
5.3 Host Commands (22) SET MULTIPLE MODE (X’C6’) This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command. The number of sectors per block is written into the Sector Count register. The IDD supports 2, 4, 8, 16 and 32 (sectors) as the block counts.
Interface At command completion (I/O registers contents to be read) 1F7H(ST) 5-68 Status information 1F6H(DH) x x x 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) Sector count/block 1F1H(ER) Error information DV xx C141-E202-01EN
5.3 Host Commands (23) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. • The device posts a status as the result of command execution only once at completion of the data transfer.
Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No. [LSB] / LBA 1F3H(SN) End sector No. / LBA [LSB] 1F2H(SC) 00 (*1) 1F1H(ER) Error information *1 5-70 L x DV End head No. / LBA [MSB] If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
5.3 Host Commands (24) WRITE DMA (X’CA’ or X’CB’) This command operates similarly to the WRITE SECTOR(S) command except for following events. • The data transfer starts at the timing of DMARQ signal assertion. • The device controls the assertion or negation timing of the DMARQ signal. • The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device.
Interface At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5H(CH) End cylinder No. [MSB] / LBA 1F4H(CL) End cylinder No. [LSB] / LBA 1F3H(SN) End sector No. / LBA [LSB] 1F2H(SC) 00 (*1) 1F1H(ER) Error information *1 5-72 Status information If the command is terminated due to an error, the remaining number of sectors of which data was not transferred is set in this register.
5.3 Host Commands (25) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer.
Interface (26) FLUSH CACHE (X’E7’) This command is used to order to write every write cache data stored by the device into the medium. BSY bit is held at "1" until every data has been written normally or an error has occurred. The device performs every error recovery so that the data are read correctly. When executing this command, the reading of the data may take several seconds if much data are to be read.
5.3 Host Commands (27) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data. After that, 512 bytes of data is transferred from the host and the device writes the data to the buffer, then generates an interrupt.
Interface (28) IDENTIFY DEVICE (X’EC’) The host system issues the IDENTIFY DEVICE command to read parameter information from the device. Upon receipt of this command, the drive sets the BSY bit to one, prepares to transfer the 256 words of device identification data to the host, sets the DRQ bit to one, clears the BSY bit to zero, and generates an interrupt. After that, the host system reads the information out of the sector buffer. Table 5.
5.3 Host Commands (29) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command.
Interface Table 5.22 Information to be read by IDENTIFY DEVICE command (1 of 2) Word Value 0 X’045A’ General Configuration *1 1 X’3FFF’ Number of Logical cylinders *2 2 X’xxxx’ Detailed Configuration *3 3 X’10’ 4-5 X’0000’ 6 X’3F’ 7-9 X’0000’ 10-19 Set by a device 20 X’0003’ Undefined 21 X’xxxx’ Buffer Size (1 LSB: 512 Bytes) ex.
5.3 Host Commands Table 5.
Interface Bit 14-8: Undefined Bit 7: Removable disk drive = 1 Bit 6: Fixed drive = 1 Bit 5-3: Undefined Bit 2: IDENTIFY DEVICE Bit 1-0: Reserved Valid = 0 *2 Word 1, 3, 6, 60-61 Word MHU2100AT 1 X ' 3FFF ' 3 X ' 10 ' 6 X ' 3F ' 60-61 X ' BA52230 ' *3 Status of the Word 2 Identify information is shown as follows: 37C8h The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete.
5.3 Host Commands *5 Word 50: Device capability Bit 15: 0 Bit 14: 1 Bit 13 to 1 Reserved Bit 0 Standby timer value '1' = Standby timer value of the device is the smallest value.
Interface *10 Word 64: Advance PIO transfer mode support status Bit 15-8: Reserved Bit 7-0: Advance PIO transfer mode Bit 1: 1 = Mode 4 Bit 0: 1 = Mode 3 *11 WORD 80 Bit 15-7: Reserved Bit 6: 1 = ATA/ATAPI-6 supported Bit 5: 1 = ATA/ATAPI-5 supported Bit 4: 1 = ATA/ATAPI-4 supported Bit 3: 1 = ATA-3 supported Bit 2: 1 = ATA-2 supported Bit 1-0: Undefined *12 WORD 82 5-82 Bit 15: Undefined Bit 14: '1' = Supports the NOP command. Bit 13: '1' = Supports the READ BUFFER command.
5.3 Host Commands *13 WORD 83 Bit 15: =0 Bit 14: =1 Bit 13: * '1' = FLUSH CACHE EXT command supported. Bit 12: '1' = FLUSH CACHE command supported. Bit 11: '1' = Device Configuration Overlay feature set supported. Bit 10:* '1' = 48 bit LBA feature set. Bit 9: '1' = Automatic Acoustic Management feature set. Bit 8: '1' = Supports the SET MAX Security extending command. Bit 7: Reserved Bit 6: '1' = When the power is turned on, spin is started by the SET FEATURES sub-command.
Interface *15 WORD 85 Bit 15: Undefined. Bit 14: '1' = Supports the NOP command. Bit 13: '1' = Supports the READ BUFFER command. Bit 12: '1' = Supports the WRITE BUFFER command. Bit 11: Undefined. Bit 10: '1' = Supports the Host Protected Area function. Bit 9: '1' = Supports the DEVICE RESET command. Bit 8: '1' = Enables the SERVICE interrupt. From the SET FEATURES command Bit 7: '1' = Enables the release interrupt.
5.3 Host Commands *17 WORD 87 Bits 15: = '0' Bits 14: = '1' Bits 13-2: Reserved Bit 1-0: Same definition as WORD 84. *18 WORD 88 Bit 15-8: Currently used Ultra DMA transfer mode Bit 13: '1' = Mode 5 is selected. Bit 12: '1' = Mode 4 is selected. Bit 11: '1' = Mode 3 is selected. Bit 10: '1' = Mode 2 is selected. Bit 9: '1' = Mode 1 is selected. Bit 8: '1' = Mode 0 is selected.
Interface Bit 10, 9: Method for deciding the device No. of Device 1. '00' = Reserved '01' = Using a jumper. '10' = Using the CSEL signal. '11' = Other method. Bit 8: Bits 7-0: = '1' (In the case of device 1) In the case of Device 0 (master drive), a valid value is set. Bit 7: Reserved Bit 6: '1' = Device 1 is selected, Device 0 responds. Bit 5: '1' = Device 0, assertion of DASP- was detected. Bit 4: '1' = Device 0, assertion of PDIAG- was detected.
5.3 Host Commands *23 WORD 128 C141-E202-01EN Bit 15-9: Reserved Bit 8: Security level.
Interface (30) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed. Upon receipt of this command, the device sets the BSY bit of the Status register and saves the parameters in the Features register. Then, the device clears the BSY bit, and generates an interrupt. If the value in the Features register is not supported or it is invalid, the device posts an ABORTED COMMAND error.
5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx or *1~3 1F1H(FR) [See Table 5.5] 1 1 1 xx At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information DV xx *1) Data Transfer Mode The host sets X’03’ to the Features register.
Interface Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) 00100 010 (X’22’: Mode 2) Ultra DMA transfer mode X 01000 000 (X’40’: Mode 0) 01000 001 (X’41’: Mode 1) 01000 010 (X’42’: Mode 2) 01000 011 (X’43’: Mode 3) 01000 100 (X’44’: Mode 4) 01000 101 (X’45’: Mode 5) *2) Advanced Power Management (APM) The host writes the Sector Count register with the desired power management level and executes this command with the Features register X’05’, and then Advanced Power Manage
5.3 Host Commands *3) Automatic Acoustic Management (AAM) The host writes to the Sector Count register with the requested acoustic management level and executes this command with subcommand code 42h, and then Automatic Acoustic Management is enabled. The AAM level setting is preserved by the drive across power on, hardware and software resets.
Interface (31) SECURITY SET PASSWORD (X’F1’) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.24 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data. (Table 5.25) Issuing this command in LOCKED MODE or FROZEN MODE returns the Aborted Command error. Table 5.
5.
Interface (32) SECURITY UNLOCK(X’F2’) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.26 to the device. Operation of the device varies as follows depending on whether the host specifies the master password. • When the master password is selected When the security level is LOCKED MODE is high, the password is compared with the master password already set. If the passwords are the same, LOCKED MODE is canceled. Otherwise, the Aborted Command error is returned.
5.
Interface (33) SECURITY ERASE PREPARE (X’F3’) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command. Issuing this command during FROZEN MODE returns the Aborted Command error.
5.3 Host Commands (34) SECURITY ERASE UNIT (X’F4’) This command erases all user data. This command also invalidates the user password and releases the lock function. The host transfers the 512-byte data shown in Table 5.26 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set. The device erases user data, invalidates the user password, and releases the lock function if the passwords are the same.
Interface (35) SECURITY FREEZE LOCK (X’F5’) This command puts the device into FROZEN MODE. The following commands used to change the lock function return the Aborted Command error if the device is in FROZEN MODE. • SECURITY SET PASSWORD • SECURITY UNLOCK • SECURITY ERASE PREPARE • SECURITY ERASE UNIT • SECURITY DISABLE PASSWORD FROZEN MODE is canceled when the power is turned off, or when hardware is resented.
5.
Interface (36) SECURITY DISABLE PASSWORD (X’F6’) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 5.26 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same. Although this command invalidates the user password, the master password is retained.
5.
Interface (37) READ NATIVE MAX ADDRESS (X’F8’) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command. Upon receipt of this command, the device sets the BSY bit and indicates the maximum address in the DH, CH, CL and SN registers. Then, it clears BSY and generates an interrupt.
5.3 Host Commands (38) SET MAX (X’F9’) SET MAX Features Register Values Value • Command 00h Obsolete 01h SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h SET MAX FREEZE LOCK 05h - FFh Reserved SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command. This command allows the maximum address accessible by the user to be set in LBA or CHS mode.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) x L x DV 1 0 0 1 Max head/LBA [MSB] 1F5H(CH) Max. cylinder [MSB]/Max. LBA 1F4H(CL) Max. cylinder [LSB]/Max. LBA 1F3H(SN) Max. sector/Max. LBA [LSB] 1F2H(SC) xx 1F1H(FR) xx VV At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) • Status information x x x DV Max head/LBA [MSB] 1F5H(CH) Max. cylinder [MSB]/Max. LBA 1F4H(CL) Max. cylinder [LSB]/Max.
5.3 Host Commands At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information Password information Words • Contents 0 Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved SET MAX LOCK (FR = 02h) The SET MAX LOCK command sets the device into SET_MAX_LOCK state.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) 02 1 0 0 1 xx At command completion (I/O registers contents to be read) • 1F7H(ST) Status information 1F6H(DH) xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information SET MAX UNLOCK (FR = 03h) This command requests a transfer of single sector of data from the host, and defines the contents of
5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) 03 1 0 0 1 xx At command completion (I/O registers contents to be read) • 1F7H(ST) Status information 1F6H(DH) xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information SET MAX FREEZE LOCK (FR = 04h) The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.
Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1F6H(DH) x x x DV 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(FR) 04 1 0 0 1 xx At command completion (I/O registers contents to be read) 5-108 1F7H(ST) Status information 1F6H(DH) xx 1F5H(CH) xx 1F4H(CL) xx 1F3H(SN) xx 1F2H(SC) xx 1F1H(ER) Error information C141-E202-01EN
5.3 Host Commands (39) READ SECTOR(S) EXT (X’24’): Option (customizing) • Description This command is the extended command of the READ SECTOR(S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the READ SECTOR(S) command.
Interface (40) READ DMA EXT (X’25’): Option (customizing) • Description This command is the extended command of the READ DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the READ DMA command.
5.3 Host Commands (41) READ NATIVE MAX ADDRESS EXT (X’27’): Option (customizing) • Description This command is used to assign the highest address that the device can initially set with the SET MAX ADDRESS EXT command. The maximum address is displayed in the CH, CL, SN registers of the device control register with HOB bit = 0, 1. • Error reporting conditions This command is issued with LBA = 0.
Interface (42) READ MULTIPLE EXT (X’29’): Option (customizing) • Description This command is the extended command of the READ MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the READ MULTIPLE command.
5.3 Host Commands (43) READ LOG EXT (X'2F') [Optional command (Customize)] • Description This command reads data from the general-purpose log of a device. The generalpurpose log includes the extended SMART comprehensive error log, extended self-test log, SMART selective self-test log, and other logs. The types of logs available depend on the customize operation. For information on the DRQ, INTRQ, and BSY protocols related to the transfer of data, see Section 5.4.1.
Interface Log address: Log number of the log to be read Sector offset: First log sector subject to the data transfer Sector count: Number of sectors to be read from the specified log If the device does not support this command, the device shall return the Command Aborted error. If the Log address value, the Sector count value, or the Sector offset value is invalid, the device shall return the Command Aborted error.
5.3 Host Commands (44) WRITE SECTOR(S) EXT (X’34’): Option (customizing) • Description This command is the extended command of the WRITE SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the WRITE SECTOR (S) command.
Interface (45) WRITE DMA EXT (X’35’): Option (customizing) • Description This command is the extended command of the WRITE DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the WRITE DMA command.
5.3 Host Commands (46) SET MAX ADDRESS EXT (X’37’): Option (customizing) • Description This command limits specifications so that the highest address that can be accessed by users can be specified only in LBA mode. The address information specified with this command is set in words 1, 54, 57, 58, 60, 61, and 100 to 103 of the IDENTIFY DEVICE command response. If read or write processing is executed for an address that is outside of the new address space, an ID Not Found error occurs.
Interface At command issuance (I/O registers setting contents) 1F7h(CM) 0 0 1 1 1F6h(DH) 1 L 1 DV 1F5h(CH) P 1F5h(CH) C 1F4h(CL) P 1F4h(CL) C 1F3h(SN) P 1F3h(SN) C SET MAX LBA (47-40) SET MAX LBA (23-16) SET MAX LBA (39-32) SET MAX LBA (15-8) SET MAX LBA (31-24) SET MAX LBA (7-0) 1F2h(SC) P xx 1F2h(SC) C xx 1F1h(FR) P xx xx 1F1h(FR) C 0 1 1 1 xx VV C: Current P: Previous At command completion (I/O registers contents to be read) 1F7h(ST) 1F6h(DH) Status information 1 L 1 DV 1F5
5.3 Host Commands (47) WRITE MULTIPLE EXT (X’39’): Option (customizing) • Description This command is the extended command of the WRITE MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the WRITE MULTIPLE command.
Interface (48) WRITE LOG EXT (X’3F’) [Optional command (Customize)] • Description This command writes data to the general-purpose log of a device. The generalpurpose log includes the extended SMART comprehensive error log, extended self-test log, SMART selective self-test log, and other logs. However, some of these logs are read-only logs. The types of logs available depend on the customize operation. For information on the DRQ, INTRQ, and BSY protocols related to the transfer of data, see Section 5.4.1.
5.3 Host Commands Log address: Log number of the log to be written Sector offset: First log sector subject to the data transfer Sector count: Number of sectors to be written to the specified log If the device does not support this command, the device shall return the Command Aborted error. If the Log address value, the Sector count value, or the Sector offset value is invalid, the device shall return the Command Aborted error.
Interface (49) READ VERIFY SECTOR(S) EXT (X’42): Option (customizing) • Description This command is the extended command of the READ VERIFY SECTOR(S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h. Other command controls are the same as those of the READ VERIFY SECTOR(S) command.
5.3 Host Commands (50) FLUSH CACHE EXT (X’EA’): Option (customizing) • Description This command executes the same operation as the Flush Cache command (E7h) but only LBA = 1 can be specified. • Error reporting conditions This command is issued with LBA = 0.
Interface 5.3.3 Error posting Table 5.27 lists the defined errors that are valid for each command. Table 5.
5.3 Host Commands Table 5.
Interface 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1. However, the following commands can be executed even if DRDY bit is 0. • EXECUTE DEVICE DIAGNOSTIC • INITIALIZE DEVICE PARAMETERS 5.4.
5.4 Command Protocol f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the BSY bit and steps d) and after are repeated. Even if an error is encountered, the device prepares for data transfer by setting the DRQ bit. Whether or not to transfer the data is determined for each host. In other words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.
Interface IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading.
5.4 Command Protocol 5.4.2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive.
Interface 40 ms Figure 5.5 WRITE SECTOR(S) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer. Note that the host does not need to read the Status register for the first and the last sector to be transferred.
5.4 Command Protocol 5.4.3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device.
Interface Figure 5.6 Protocol for the command execution without data transfer 5.4.4 Other commands • READ MULTIPLE (EXT) • WRITE MULTIPLE (EXT) • SLEEP See the description of each command. 5.4.5 DMA data transfer commands • READ DMA (EXT) • WRITE DMA (EXT) • INDENTIFY DEVICE DMA Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.
5.4 Command Protocol f) When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads the Status register. g) The host resets the DMA channel. Figure 5.7 shows the correct DMA data transfer protocol. f g d d f e Figure 5.
Interface 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g.: Command Block Register access).
5.5 Ultra DMA Feature Set Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.
Interface 7) The host shall release DD (15:0) within tAZ after asserting DMACK-. 8) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst. 9) The host shall negate STOP and assert HDMARDY- within tENV after asserting DMACK-.
5.5 Ultra DMA Feature Set 2) The device shall pause an Ultra DMA burst by not generating DSTROBE edges. NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait tRP before asserting STOP. 3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.
Interface 6) The host shall drive DD (15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5): 7) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
5.5 Ultra DMA Feature Set 4) If the host negates HDMARDY- within tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDY- greater than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device.
Interface 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated. 2) The device shall assert DMARQ to initiate an Ultra DMA burst. 3) Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert STOP.
5.5 Ultra DMA Feature Set 5.5.4.2 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements): 1) The host shall drive a data word onto DD (15:0). 2) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than tCYC for the selected Ultra DMA Mode.
Interface 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges. 2) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge.
5.5 Ultra DMA Feature Set b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred. 2) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.
Interface 13) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command. a) Both the host and the device shall have a 16-bit CRC calculation function.
5.5 Ultra DMA Feature Set i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last. 5.5.
Interface 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. t0 Addresses t1 t9 t2 DIOR-/DIOW- t2i Write data DD0-DD15 t3 t4 Read data DD0-DD15 t5 t6 t10 IORDY t11 t12 Symbol Timing parameter Min. Max.
5.6 Timing 5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. DMACKtI DIOR-/DIOWtD Symbol Timing parameter Min. Max.
Interface 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.23 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
5.6 Timing 5.6.3.2 Ultra DMA data burst timing requirements Table 5.29 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX t2CYCTYP 240 160 120 90 60 40 tCYC 112 73 54 39 25 16.
Interface Table 5.
5.6 Timing Table 5.30 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) NAME COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tDSIC 14.7 9.7 6.8 6.8 4.8 2.3 Recipient IC data setup time (from data valid until STROBE edge) (*1) tDHIC 4.8 4.8 4.8 4.8 4.8 2.8 Recipient IC data hold time (from STROBE edge until data may become invalid) (*1) tDVSIC 72.9 50.9 33.9 22.6 9.
Interface 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
5.6 Timing 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK(host) tRP STOP (host) HDMARDY(host) tRFS DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY- is negated. 2) After negating HDMARDY-, the host may receive zero, one, two or three more data words from the device. Figure 5.
Interface 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tMLI DMACK(host) STOP (host) tACK tLI tLI tACK tLI HDMARDY(host) tSS tIORDYZ DSTROBE (device) tZAH tAZ DD(15:0) tCVS tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6 Timing 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tLI tMLI DMACK(host) tAZ tRP tZAH tACK STOP (host) tACK HDMARDY(host) tRFS tLI tMLI tIORDYZ DSTROBE (device) tCVS DD(15:0) tCVH CRC tACK DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
Interface 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) tUI DMACK(host) tACK tENV STOP (host) tZIORDY tLI tUI DDMARDY(device) tACK HSTROBE (host) tDZFS tDVS tDVH DD(15:0) (host) tACK DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect until DMARQ and DMACK- are asserted. Figure 5.
5.6 Timing 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.
Interface 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. tRP DMARQ (device) DMACK(host) STOP (host) DDMARDY(device) tRFS HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY- is negated. 2) After negating DDMARDY-, the device may receive zero, one two or three more data words from the host. Figure 5.
5.6 Timing 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. tLI DMARQ (device) tMLI DMACK(host) tLI tACK tSS STOP (host) tLI tIORDYZ DDMARDY(device) tACK HSTROBE (host) tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
Interface 5.6.3.11 Device terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK(host) tLI tACK tMLI STOP (host) tRP tIORDYZ DDMARDY(device) tRFS HSTROBE (host) tLI tMLI tACK tCVS DD(15:0) (host) tCVH CRC tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated. Figure 5.
5.6 Timing 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESETSoftware reset tM tN BSY DASPtP *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device] tN BSY DASP[Slave device] BSY tQ tP PDIAG- tS DASPtR Symbol Timing parameter Min. Max.
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CHAPTER 6 Operations 6.1 Device Response to the Reset 6.2 Power Save 6.3 Defect Processing 6.4 Read-ahead Cache 6.
Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for least 500 ms to confirm presence of a slave device (device 1).
6.1 Device Response to the Reset Power on Master device Power On ResetStatus Reg. BSY bit Max. 31 sec. Checks DASP- for up to 500 ms. If presence of a slave device is confirmed, PDIAG- is checked for up to 31 seconds. Slave device Power On ResetBSY bit Max. 1 ms. PDIAG- Max. 30 sec. DASPMax. 450 ms. Figure 6.1 Response to power-on Note: Figure 6.1 has a assumption that the device is kept on the power-off condition for more than 5 sec before the device power is turned on. 6.1.
Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below: DASP- signal: Asserted within 450 ms. PDIAG- signal: Negated within 1 ms and asserted within 30 seconds. The asserted PDIAG-signal is negated 30 seconds after it is asserted if the command is not received. ResetMaster device Status Reg. BSY bit Max. 31 sec. Checks DASP- for up to 500 ms.
6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.
Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAGsignal for up to 6 seconds to see if the slave device has completed the selfdiagnosis successfully. The master device does not check the DASP- signal.
6.2 Power Save 6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power save mode There are five types of power consumption state of the device including active mode where all circuits are active. • Active mode • Active idle mode • Low power idle mode • Standby mode • Sleep mode The device enters the active idle mode by itself. The device also enters the idle mode in the same way after power-on sequence is completed.
Operations • Upon receipt of a hard reset • Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the spindle motor has stopped from the low power idle state. The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active, active idle, or low power idle mode because the access to the disk medium cannot be made immediately.
6.3 Defect Processing 6.2.2 Power commands The following commands are available as power commands. • IDLE • IDLE IMMEDIATE • STANDBY • STANDBY IMMEDIATE • SLEEP • CHECK POWER MODE • SET FEATURES (APM setting) 6.3 Defect Processing This device performs alternating processing where the defective sector is alternated with the spare area depending on media defect location information.
Operations 6.3.2 Alternating processing for defective sectors The following two types of technology are used for alternating processing: (1) Sector slip processing In this method, defective sectors are not used (thereby avoiding the effects of defects), and each defective sector is assigned to the next contiguous sector that is normal. Depending on the format defined at shipment from the plant, this processing is performed for defective sectors. Figure 6.
6.3 Defect Processing (3) Automatic alternating processing This technology assigns a defective sector to a spare sector of an spare cylinder for alternate assignment. This device performs automatic alternating processing in the event of any of the following errors. • Automatic alternating processing is attempted for read error recovery by reaching the specified retry cycle while a read error retry is in progress.
Operations 6.4 Read-ahead Cache Read-ahead Cache is the function for automatically reading data blocks upon completion of the read command in order to read data from disk media and save data block on a data buffer. If a subsequent command requests reading of the read-ahead data, data on the data buffer can be transferred without accessing the disk media. As the result, faster data access becomes possible for the host. 6.4.1 DATA buffer structure This device contains a data buffer.
6.4 Read-ahead Cache 6.4.2 Caching operation The caching operation is performed only when the commands listed below are received. If any of the following data are stored on the data buffer, the data is sent to the host system. • All of the sector data that this command processes. • A part of the sector data including the start sector, that this command processes. If part of the data to be processed is stored on the data buffer, the remaining data is read from disk media and sent to the host system.
Operations 1)-1 Any command other than the following commands is issued. (All cachingtarget data is invalidated.) RECALIBRATE READ LONG WRITE LONG IDLE IMMEDIATE DOWNLOAD MICROCODE DEVICE CONFIGURATION READ BUFFER WRITE BUFFER SET FEATURES SECURITY ERASE UNIT READ LOG EXT WRITE LOG EXT UNSUPPORT COMMAND (INVALID COMMAND) 1)-2 Commands that partially invalidate caching data (When data in the buffer or on media is overwritten, the overwritten data is invalidated.
6.4 Read-ahead Cache 6.4.3 Using the read segment buffer Methods of using the read segment buffer are explained for following situations. 6.4.3.1 Miss-hit In this situations, the top block of read requested data is not stored at all in the data buffer. As a result, all of the read requested data is read from disk media. 1) HAP (host address pointer) and DAP (disk address pointer) are defined in the head of the segment allocated from Buffer.
Operations 6.4.3.2 Sequential Hit When the read command that is targeted at a sequential address is received after execution of the read commands is completed, the read command transmits the Read requested data to the host system continuing read-ahead without newly allocating the buffer for read. 1) When the sequential read command is received, HAP is set in the sequential address of the last read command, and DAP is set at a present read position as it is.
6.4 Read-ahead Cache 6.4.3.3 Full hit In this situation, all read requested data is stored in the data buffer. Transfer of the read requested data is started from the location where hit data is stored. For data that is a target of caching and remains before a full hit, the data is retained when execution of the command is completed. This is done so that a new readahead operation is not performed.
Operations 6.4.3.4 Partial hit In this situation, a part of read requested data including the top sector is stored in the data buffer. A transfer of the read requested data starts from the address where the data that is hit is stored until the top sector of the read requested data. Remaining part of insufficient data is read then. An example is a case where a partial hit occurs in cache data, as shown below.
6.5 Write Cache 6.5 Write Cache Write Cache is the function for reducing the command processing time by separating command control to disk media from write control to disk media. When Write Cache is permitted, the write command can be keep receiving as long as the space available for data transfers remains free on the data buffer. Because of this function, command processing appears to be completed swiftly from the viewpoint of the host. It improves system throughput. 6.5.
Operations (3) Status report in the event of an error The status report concerning an error occurring during writing onto media is created when the next command is issued. Where the command reporting the error status is not executed, only the error status is reported. Only the status of an error that occurs during write processing is reported. The error status is not reported in the following case: • The reset command is received after an error has occurred during writing to media.
6.5 Write Cache IMPORTANT If Write Cache is enabled, there is a possibility that data transferred from the host with the Write Cache enable command is not completely written on disk media before the normal end interrupt is issued. If an unrecoverable error occurs while multiple commands that are targets of write caching are received, the host has difficulty determining which command caused the error.
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Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors. Interfaces based on this standard are called ATA interfaces.
Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. VCM Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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Acronyms and Abbreviations HDD Hard disk drive A ABRT AIC AMNF ATA AWG Aborted command Automatic idle control Address mark not found AT attachment American wire gage B BBK BIOS Bad block detected Basic input-output system C CORR CH CL CM CSR CSS CY Corrected data Cylinder high register Cylinder low register Command register Current sense register Current start/stop Cylinder register I IDNF IRQ14 L LED dB A-scale weighting Disk enclosure Device/head register Drive ready Data request bit Drive seek
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Index 1 drive connection ..................................... 2-3 2 drives configuration................................ 2-4 2 drives connection.................................... 2-4 8MB buffer .............................................. 6-12 A A/D converter circuit............................... 4-11 AAM........................................................ 5-91 acceleration mode.................................... 4-19 acoustic noise ............................................
Index data that is a target of caching .................6-13 data transfer mode....................................5-89 data-surface servo format ........................4-15 defect processing .......................................6-9 description ..................... 5-109, 5-110, 5-111, 5-112, 5-113, 5-115, 5-116, 5-117, 5-119, 5-120, 5-122, 5-123 device configuration ...........................2-1, 2-2 DEVICE CONFIGURATION.................5-59 DEVICE CONFIGURATION FREEZE LOCK ...........................
Index Fujitsu Internal Use Only I I/O register................................................. 5-7 IDENTIFY DEVICE............................... 5-76 IDENTIFY DEVICE DMA..................... 5-77 IDLE.................................................5-38, 6-9 IDLE IMMEDIATE .........................5-36, 6-9 Information to be read by IDENTIFY DEVICE command.....................5-78, 5-79 INITIALIZE DEVICE PARAMETERS................................... 5-32 INITIALIZE DEVICE PARAMETERS command ............
Index R raw attribute value ...................................5-49 READ BUFFER ......................................5-73 read circuit ...............................................4-10 READ DMA ............................................5-69 READ DMA (EXT).................................6-12 READ DMA EXT .................................5-110 READ LOG EXT ..................................5-113 READ LONG ..........................................5-23 READ MULTIPLE..................................
Index Fujitsu Internal Use Only STANDBY command ............................... 6-8 STANDBY IMMEDIATE ...............5-35, 6-9 STANDBY IMMEDIATE command........ 6-8 standby mode............................................. 6-8 start mode ................................................ 4-19 status........................................................ 5-55 status flag................................................. 5-49 status register...........................................
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Comment Form We would appreciate your comments and suggestions regarding this manual. Manual code C141-E202-01EN Manual name MHU2100AT DISK DRIVE PRODUCT MANUAL Please mark each item: E(Excellent), G(Good), F(Fair), P(Poor). General appearance Technical level Organization Clarity Accuracy ( ( ( ( ( ) ) ) ) ) Illustration Glossary Acronyms & Abbreviations Index ( ( ( ( ) ) ) ) Comments & Suggestions List any errors or suggestions for improvement.
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MHU2100AT DISK DRIVE PRODUCT MANUAL MHU2100AT DISK DRIVE PRODUCT MANUAL C141-E202-01EN C141-E202-01EN
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