Datasheet

© Copyright 2009 Future Technology Devices International Ltd
11
Document Reference No.: FT_000202
UM245R USB - Parallel FIFO Development Module Datasheet Version 1.04
Clearance No.: FTDI# 124
4.5 FT245 FIFO Control Interface Write Cycle Timing Diagrams
Figure 4.3 FIFO Write Cycle
Time
Description
Min
Max
Unit
T7
WR Active Pulse Width
50
ns
T8
WR to RD Pre-Charge Time
50
ns
T9
Data Setup Time before WR Inactive
20
ns
T10
Data Hold Time from RD Inactive
0
ns
T11
WR Inactive to TXE#
0
25
ns
T12
TXE# Inactive After WR Cycle
80
ns
Table 4.5 FIFO Write Cycle Timings