Datasheet

Page7
T6
3.10 POWER GOOD SIGNAL Time sequence
Measure condition :230V (FULL LOAD)
PS-ON
90%
10%
DC OUTPUT
T4
P.G. SIGNAL
T2 T3
Figure 1
T1: PS_ON -- DC O/P within Spec.＜500mS
T2: RISETIME < 20mS
T3: Power Good Delay Time 100mS-500mS
T4: Power Good Rise-time＜10mS
T5: AC fail hold-up time＞16mS
T6: Power Fail Delay Time＞1mS
3.11 Output Transient Response
Expected output transient step sizes for each output. The transient load slew
rate is = 1.0 A/µs.
Table of DC Output Transient Step Sizes
Output
Max. step size
(% of rated output amps per Sec 3.1)
+12V1 4A (1200uF)
+12 V2 4A (1000uF)
+5 V 4A (1000uF)
+3.3 V 6A (680uF)
-12 V 0.12A (350uF)
+5 VSB 0.625A (350uF)
(Adding external capactor)
Output voltages should remain within the regulation limits of Section 4.1,
and the power supply should be stable when subjected to load transients per
above table from any steady state load, including any or all of the following
conditions:
• Load-changing repetition rate of 50 Hz to 10 kHz
T5
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T1
AC