Datasheet

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T1: PS_ON -- DC O/P within Spec.500mS
T2: RISETIME < 20mS
T3: Power Good Delay Time 100mS-500mS
T4: Power Good Rise-time10mS
T5: AC fail hold-up time17mS
T6: Power Fail Delay Time1mS
3.11 Output Transient Response
Expected output transient step sizes for each output. The transient load slew
rate is = 1.0 A/µs.
Table of DC Output Transient Step Sizes
Output Max. step size
+12V 4A
+5 V 4A
+3.3 V 4A
-12 V 0.1A
+5 VSB 0.25A
(Adding external capactor of Section 3.12)
Output voltages should remain within the regulation limits of Section 3.1,
and the power supply should be stable when subjected to load transients per
above table from any steady state load, including any or all of the following
conditions:
• Load-changing repetition rate of 50 Hz to 10 kHz
•AC input range per Section 2.0
3.12 Capacitive Load
The power supply should be able to power up and operate normally with
the following capacitances simultaneously present on the DC outputs. This
capacitive loading should be used to check all of function test, but without
hold-up time.
Output
ATX12V
Capacitive load (uF)
+12 V 10000
+5 V 5000
+3.3 V 5000
-12 V 350
+5 VSB 3000
3.13 Closed-loop Stability
The power supply shall be unconditionally stable under all
line/load/transient load conditions including capacitive loads specified in
Section 3.13. A minimum of 45 degrees phase margin and 10 dB gain margin
is recommended at both the maximum and minimum loads.
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7/9禁止翻印外洩 ESD10049826-R6.pdf 發行時間:2011/4/18 3:57 下午