Datasheet

MC68HC908QY4MC68HC908QT4MC68HC908QY2MC68HC908QT2MC68HC908QY1MC68HC908QT1
92 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM)
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7.7.2.3 Interrupt Status Register 3
IF15 Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 17 Always read 0
7.7.3 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.7.4 Break Interrupts
The break module can stop normal program flow at a software
programmable break point by asserting its break interrupt output. (See
Section 17. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
Address: $FE06
Bit 7654321Bit 0
Read: 0 0 00000IF15
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 7-14. Interrupt Status Register 3 (INT3)