Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
84 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM)
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7.5.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
7.5.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST
pin for all internal
reset sources.
7.5.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the V
DD
voltage falls to the
LVI trip voltage V
Trip
. The LVI bit in the SIM reset status register (SRSR)
is set, and the external reset pin (RST
) is held low while the SIM counter
counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later,
the CPU and memories are released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the (RST) pin for all
internal reset sources.