Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
82 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM)
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Figure 7-6. Sources of Internal Reset
NOTE: For POR resets, the SIM cycles through 4096 BUSCLKX4 cycles during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST
shown in Figure 7-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7.5.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power on has occurred. The
external reset pin (RST
) is held low while the SIM counter counts out
4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU
and memories are released from reset to allow the reset vector
sequence to occur.
At power on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive BUSCLKX4.
• Internal clocks to the CPU and modules are held inactive for 4096
BUSCLKX4 cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
See Figure 7-7.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET