Datasheet

System Integration Module (SIM)
Reset and System Initialization
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA System Integration Module (SIM) 81
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minimum of 67 BUSCLKX4 cycles, assuming that the POR was not the
source of the reset. See Table 7-2 for details. Figure 7-4 shows the
relative timing.
Figure 7-4. External Reset Timing
7.5.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST
pin low for 32 BUSCLKX4
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see
Figure 7-5). An internal reset can be caused by an illegal address, illegal
opcode, COP time out, LVI, or POR (see Figure 7-6).
Figure 7-5. Internal Reset Timing
Table 7-2. PIN Bit Set Timing
Reset Type Number of Cycles Required to Set PIN
POR 4163 (4096 + 64 + 3)
All others 67 (64 + 3)
RST
ADDRESS BUS PC
VECT H VECT L
BUSCLKX2
IRST
RST
RST PULLED LOW BY MCU
ADDRESS
32 CYCLES 32 CYCLES
VECTOR HIGH
BUSCLKX4
BUS