Datasheet

System Integration Module (SIM)
RST and IRQ Pins Initialization
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA System Integration Module (SIM) 79
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7.3 RST and IRQ Pins Initialization
RST and IRQ pins come out of reset as PTA3 and PTA2 respectively.
RST and IRQ functions can be activated by programing CONFIG2
accordingly. Refer to Section 5. Configuration Register (CONFIG).
7.4 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, BUSCLKX2, as shown in Figure 7-3.
Figure 7-3. SIM Clock Signals
7.4.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(BUSCLKX4) divided by four.
7.4.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 BUSCLKX4 cycle POR time out has completed. The RST pin
is driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the time out.
÷ 2
BUS CLOCK
GENERATORS
SIM
SIM COUNTER
FROM
OSCILLATOR
FROM
OSCILLATOR
BUSCLKX2
BUSCLKX4