Datasheet

System Integration Module (SIM)
Introduction
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA System Integration Module (SIM) 77
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Figure 7-1. SIM Block Diagram
Table 7-1. Signal Name Conventions
Signal Name Description
BUSCLKX4 Buffered clock from the internal, RC or XTAL oscillator circuit.
BUSCLKX2
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM
to generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
Address bus Internal address bus
Data bus Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W
Read/write signal
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
÷2
LVI RESET (FROM LVI MODULE)
V
DD
INTERNAL
PULL-UP
FORCED MON MODE ENTRY (FROM MENRST MODULE)