Datasheet

Central Processor Unit (CPU)
CPU Registers
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Central Processor Unit (CPU) 63
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6.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and 5
are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit
15
1413121110987654321
Bit
0
Read:
Write:
Reset: Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
Bit 7654321Bit 0
Read:
V11HINZC
Write:
Reset:X11X1XXX
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)