Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1

58 Configuration Register (CONFIG) MOTOROLA

Configuration Register (CONFIG)

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LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit

LVI5OR3 selects the voltage operating mode of the LVI module. The

voltage mode selected for the LVI should match the operating V

for

the LVI’s voltage trip points for each of the modes.

1 = LVI operates in 5-V mode

0 = LVI operates in 3-V mode

NOTE: The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other

resets will leave this bit unaffected.

SSREC — Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of

32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay.

1 = Stop mode recovery after 32 BUSCLKX4 cycles

0 = Stop mode recovery after 4096 BUSCLKX4 cycles

NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery.

When using the LVI during normal operation but disabling during stop

mode, the LVI will have an enable time of t

. The system

stabilization time for power-on reset and long stop recovery (both

4096 BUSCLKX4 cycles) gives a delay longer than the LVI enable

time for these startup scenarios. There is no period where the MCU is

not protected from a low-power condition. However, when using the

short stop recovery configuration option, the 32 BUSCLKX4 delay

must be greater than the LVI’s turn on time to avoid a period in startup

where the LVI is not protecting the MCU.

STOP — STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled

0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit

COPD disables the COP module.

1 = COP module disabled

0 = COP module enabled