Datasheet

Memory
Input/Output (I/O) Section
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Memory 41
NON-DISCLOSURE AGREEMENT REQUIRED
$FE0C
LVI Status Register
(LVISR)
See page 199.
Read: LVIOUT 0 00000R
Write:
Reset:00000000
$FE0D
↓
$FE0F
Reserved for FLASH Test RRRRRRRR
Reserved for FLASH Test RRRRRRRR
$FFB0
↓
$FFBD
Unimplemented
Unimplemented
$FFBE
FLASH Block Protect
Register (FLBPR)
See page 53.
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1
0
Write:
Reset:00000000
$FFBF Unimplemented
$FFC0
Internal Oscillator Trim
Value (Optional)
Read:
TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1 TRIM0
Write:
Reset:10000000
$FFC1 Reserved RRRRRRRR
$FFC2
↓
$FFCF
Unimplemented
Unimplemented
$FFFF
COP Control Register
(COPCTL)
See page 192.
Read: LOW BYTE OF RESET VECTOR
Write: WRITING CLEARS COP COUNTER (ANY VALUE)
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 6)