Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
218 Electrical Specifications MOTOROLA
Electrical Specifications
NON-DISCLOSURE AGREEMENT REQUIRED
18.10 3-V Control Timing
Low-voltage inhibit reset, trip rising voltage
V
TRIPR
2.50 2.65 2.80 V
Low-voltage inhibit reset/recover hysteresis
V
HYS
— 60 — mV
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. All ports configured as inputs. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
OP
= 4 MHz); all inputs 0.2 V from rail; no dc loads; less than
100 pF on all outputs.
5. All ports configured as inputs. All ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured
as inputs with pullups enabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
DD
is reached.
8. R
PU1
and R
PU2
are measured at V
DD
= 5.0 V
Characteristic
(1)
Symbol Min
Typ
(2)
Max Unit
Characteristic
(1)
Symbol Min Max Unit
Internal operating frequency
(2)
f
OP
— 4MHz
RST
input pulse width low
(3)
t
IRL
1.5 — µs
1. V
DD
= 2.7 to 3.3 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.