Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
20 List of Figures MOTOROLA
List of Figures
NON-DISCLOSURE AGREEMENT REQUIRED
Figure Title Page
7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .89
7-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .91
7-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .91
7-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .92
7-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . .94
7-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .94
7-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7-19 Stop Mode Recovery from Interrupt . . . . . . . . . . . . . . . . . . . . .96
7-20 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .96
7-21 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . .98
7-22 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . .99
8-1 XTAL Oscillator External Connections . . . . . . . . . . . . . . . . . .106
8-2 RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . .107
8-3 Oscillator Status Register (OSCSTAT). . . . . . . . . . . . . . . . . .111
8-4 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . .112
9-1 Monitor Mode Circuit (External Clock, No High Voltage) . . . .116
9-2 Monitor Mode Circuit (Internal Clock, No High Voltage). . . . .116
9-3 Monitor Mode Circuit (External Clock, with High Voltage) . . .117
9-4 Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .119
9-5 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
9-6 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
9-7 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9-8 Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9-9 Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .127
9-10 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .128
10-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .132
10-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .136
10-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .141
10-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .144
10-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .144
10-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . .145