Datasheet

Low-Voltage Inhibit (LVI)
LVI Status Register
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Low-Voltage Inhibit (LVI) 199
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16.5 LVI Status Register
The LVI status register (LVISR) indicates if the V
DD
voltage was
detected below the V
TRIPF
level while LVI resets have been disabled.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
voltage falls below the
V
TRIPF
trip voltage and is cleared when V
DD
voltage rises above
V
TRIPR
. The difference in these threshold levels results in a hysteresis
that prevents oscillation into and out of reset (see Table 16-1). Reset
clears the LVIOUT bit.
Address: $FE0C
Bit 7654321Bit 0
Read: LVIOUT 000000R
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 16-2. LVI Status Register (LVISR)
Table 16-1. LVIOUT Bit Indication
V
DD
LVIOUT
V
DD
> V
TRIPR
0
V
DD
< V
TRIPF
1
V
TRIPF
< V
DD
< V
TRIPR
Previous value