Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
198 Low-Voltage Inhibit (LVI) MOTOROLA
Low-Voltage Inhibit (LVI)
NON-DISCLOSURE AGREEMENT REQUIRED
16.4.2 Forced Reset Operation
In applications that require V
DD
to remain above the V
TRIPF
level,
enabling LVI resets allows the LVI module to reset the MCU when V
DD
falls below the V
TRIPF
level. In the configuration register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
16.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
DD
fall below V
TRIPF
), the LVI
will maintain a reset condition until V
DD
rises above the rising trip point
voltage, V
TRIPR
. This prevents a condition in which the MCU is
continually entering and exiting reset if V
DD
is approximately equal to
V
TRIPF
. V
TRIPR
is greater than V
TRIPF
by the hysteresis voltage, V
HYS
.
16.4.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is
configured for 5-V or 3-V protection.
NOTE: The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (V
TRIPF
[5 V] or V
TRIPF
[3 V]) may be lower than
this. See 18.6 5-V DC Electrical Characteristics and
18.9 3-V DC Electrical Characteristics for the actual trip point voltages.