Datasheet

Low-Voltage Inhibit (LVI)
Functional Description
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Low-Voltage Inhibit (LVI) 197
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mode bit, LVISTOP, enables the LVI to operate in stop mode. Setting the
LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage,
V
TRIPF
, to be configured for 5-V operation. Clearing the LVI5OR3 bit
enables the trip point voltage, V
TRIPF
, to be configured for 3-V operation.
The actual trip thresholds are specified in 18.6 5-V DC Electrical
Characteristics and 18.9 3-V DC Electrical Characteristics.
NOTE: After a power-on reset, the LVI’s default mode of operation is 3 volts. If
a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5-V operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on
reset while the V
DD
supply is not above the V
TRIPR
for 5-V mode, the
microcontroller unit (MCU) will immediately go into reset. The next time
the LVI releases the reset, the supply will be above the V
TRIPR
for 5-V
mode.
Once an LVI reset occurs, the MCU remains in reset until V
DD
rises
above a voltage, V
TRIPR
, which causes the MCU to exit reset. See
Section 7. System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the
LVI status register (LVISR) and can be used for polling LVI operation
when the LVI reset is disabled.
16.4.1 Polled LVI Operation
In applications that can operate at V
DD
levels below the V
TRIPF
level,
software can monitor V
DD
by polling the LVIOUT bit. In the configuration
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.