Datasheet

Computer Operating Properly (COP)
Interrupts
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Computer Operating Properly (COP) 193
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15.6 Interrupts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mode
The COP is disabled in monitor mode when V
TST
is present on the IRQ
pin.
15.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
15.8.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter.
15.8.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM
counter. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
15.9 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when
BDCOP bit is set in break auxiliary register (BRKAR).