Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
192 Computer Operating Properly (COP) MOTOROLA
Computer Operating Properly (COP)
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15.4.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
15.4.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
15.4.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register (CONFIG). See Section 5. Configuration
Register (CONFIG).
15.4.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register 1 (CONFIG1). See Section 5.
Configuration Register (CONFIG).
15.5 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and
overlaps the reset vector. Writing any value to $FFFF clears the COP
counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Address: $FFFF
Bit 7654321Bit 0
Read: LOW BYTE OF RESET VECTOR
Write: CLEAR COP COUNTER
Reset: Unaffected by reset
Figure 15-2. COP Control Register (COPCTL)