Datasheet

Computer Operating Properly (COP)
I/O Signals
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Computer Operating Properly (COP) 191
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NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 × BUSCLKX4 cycles and sets
the COP bit in the reset status register (RSR). See 7.9.1 SIM Reset
Status Register.
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
15.4 I/O Signals
The following paragraphs describe the signals shown in Figure 15-1.
15.4.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is
equal to the crystal frequency or the RC-oscillator frequency.
15.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 15.5 COP
Control Register) clears the COP counter and clears bits 12–5 of the
SIM counter. Reading the COP control register returns the low byte of
the reset vector.
15.4.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter
4096 × BUSCLKX4 cycles after power up.