Datasheet

MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
190 Computer Operating Properly (COP) MOTOROLA
Computer Operating Properly (COP)
NON-DISCLOSURE AGREEMENT REQUIRED
15.3 Functional Description
Figure 15-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
18
– 2
4
or 2
13
– 2
4
BUSCLKX4 cycles; depending on the state of the
COP rate select bit, COPRS, in configuration register 1. With a 2
18
– 2
4
BUSCLKX4 cycle overflow option, a 8-MHz crystal gives a COP timeout
period of 32.766 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 12–5 of the SIM counter.
COPCTL WRITE
BUSCLKX4
RESET VECTOR FETCH
SIM RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES
(1)
SIM MODULE
CLEAR STAGES 5–12
12-BIT SIM COUNTER
CLEAR ALL STAGES
COPD (FROM CONFIG1)
RESET
COPCTL WRITE
CLEAR
COP MODULE
COPEN (FROM SIM)
COP COUNTER
1. See Section 7. System Integration Module (SIM) for more details.
COP CLOCK
COP TIMEOUT
COP RATE SELECT
(COPRS FROM CONFIG1)
6-BIT COP COUNTER