Datasheet

External Interrupt (IRQ)
IRQ Module During Break Interrupts
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA External Interrupt (IRQ) 175
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is a logic 1, regardless of the actual level on the pin. Conversely, when
the IRQ function is enabled, bit 2 of the port A data register will always
read a logic 0.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
An internal pullup resistor to V
DD
is connected to the IRQ pin; this can
be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
13.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can
be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear the latches during the break
state. See Section 7. System Integration Module (SIM).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
13.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module, see Section 5. Configuration Register
(CONFIG).
The ISCR has the following functions:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ and interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin