Datasheet

External Interrupt (IRQ)
Functional Description
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA External Interrupt (IRQ) 173
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The external interrupt pin is falling-edge-triggered and is software-
configurable to be either falling-edge or falling-edge and low-level
triggered. The MODE1 bit in the ISCR controls the triggering sensitivity
of the IRQ pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request
remains set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level triggered, the
CPU interrupt request remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK1 bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks
all interrupt requests, including external interrupt requests.
See 7.7 Exception Control.
Figure 13-2 provides a summary of the IRQ I/O register.
Addr.Register Name Bit 7654321Bit 0
$001D
IRQ Status and Control
Register
(INTSCR)
See page 176.
Read: 0 0 0 0 IRQF1 0
IMASK1 MODE1
Write:
ACK1
Reset:00000000
= Unimplemented
Figure 13-2. IRQ I/O Register Summary