Datasheet

Input/Output (I/O) Ports
Port B
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Input/Output (I/O) Ports 169
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When DDRBx is a logic 1, reading address $0001 reads the PTBx data
latch. When DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 12-2 summarizes the operation
of the port B pins.
12.4.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software
configurable pullup device for each of the eight port B pins. Each bit is
individually configurable and requires the corresponding data direction
register, DDRBx, be configured as input. Each pullup device is
automatically and dynamically disabled when its corresponding DDRBx
bit is configured as output.
Table 12-2. Port B Pin Functions
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Accesses to DDRB Accesses to PTB
Read/Write Read Write
0
X
(1)
1. X = don’t care
Input, Hi-Z
(2)
2. Hi-Z = high impedance
DDRB7–DDRB0 Pin
PTB7–PTB0
(3)
3. Writing affects data register, but does not affect the input.
1 X Output DDRB7–DDRB0 Pin PTB7–PTB0
Address: $000C
Bit 7654321Bit 0
Read:
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0
Write:
Reset:00000000
= Unimplemented
Figure 12-9. Port B Input Pullup Enable Register (PTBPUE)