Datasheet

Input/Output (I/O) Ports
Port A
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Input/Output (I/O) Ports 165
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Figure 12-4 shows the port A I/O logic.
Figure 12-4. Port A I/O Circuit
NOTE: Figure 12-4 does not apply to PTA2
When DDRAx is a logic 1, reading address $0000 reads the PTAx data
latch. When DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTERNAL DATA BUS
30 k
PTAPUEx
TO KEYBOARD INTERRUPT CIRCUIT